AD5628 datasheet(7/24 Pages) AD

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Preliminary Technical Data

AD5628/AD5648/AD5668

Rev. PrA| Page 7 of 24

RL=2 kΩ

DC Output Impedance

0.5

Ω

Short Circuit Current

VDD=+3V

Power-Up Time

µs

Coming Out of Power-Down Mode.

VDD=+3V

REFERENCE INPUTS3

Reference Input voltage

VDD

±1% for specified performance

Reference Current

µ A

VREF = VDD = +3.6V (per DAC

channel)

Reference Input Range

VDD

Reference Input Impedance

14.6

kΩ

Per DAC channel

REFERENCE OUTPUT

Output Voltage

AD5628/AD5648/AD5668x-

1.248

1.25

1.252

1.248

1.25

1.252

Reference TC

±10

ppm/°C

Reference Output

Impedance

kΩ

LOGIC INPUTS3

Input Current

±1

µA

VINL, Input Low Voltage

0.8

VDD=+3 V

VINH, Input High Voltage

VDD=+3 V

Pin Capacitance

POWER REQUIREMENTS

VDD

2.7

3.6

2.7

3.6

All Digital Inputs at 0 or VDD

IDD (Normal Mode)8

DAC Active and Excluding Load

Current

VDD=2.7 V to +3.6 V

VIH=VDD and VIL=GND

IDD (All Power-Down

Modes)9

VDD=2.7 V to +3.6 V

0.2

µA

VIH=VDD and VIL=GND

POWER EFFICIENCY

IOUT/IDD

ILOAD=2 mA, VDD=+5 V

AC CHARACTERISTICS1

(VDD = +2.7 V to +3.6 V; RL = 2 kΩ to GND; CL = 200 pF to GND; External REFIN = VDD; all specifications TMIN to TMAX unless otherwise

noted)

Parameter2

Min

Typ

Max

Unit

B Version 1

Conditions/Comments

Output Voltage Settling Time

AD5628

µs

¼ to ¾ scale settling to ±2LSB

AD5648

µs

¼ to ¾ scale settling to ±2LSB

AD5668

µs

¼ to ¾ scale settling to ±2LSB

Settling Time for 1LSB Step

Slew Rate

1.5

V/µs

Digital-to-Analog Glitch Impulse

nV-s

1 LSB Change Around Major Carry. See Figure 21.

Channel –to-Channel Isolation

100

Digital Feedthrough

0.5

nV-s

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