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AD5628/AD5648/AD5668

Preliminary Technical Data

Rev.PrA | Page 16 of 24

GENERAL DESCRIPTION

D/A Section

The AD5628/AD5648/AD5668 DACs are fabricated on a

CMOS process. The architecture consists of a string DAC

followed by an output buffer amplifier. The parts include an

internal 1.25/2.5V, 10ppm/°C reference with an internal gain of

two. Figure 22 shows a block diagram of the DAC architecture.

VOUT

OUTPUT

AMPLIFIER

(Gain=2)

VDD

GND

RESISTOR

STRING

REF (+)

REF ()

DAC REGISTER

Figure 22. DAC Architecture

Since the input coding to the DAC is straight binary, the ideal

output voltage is given by:

⎟

⎠

⎞

⎜

⎝

⎛

ext

Vref

OUT

)

(

⎟

⎠

⎞

⎜

⎝

⎛

∗

Vref

OUT

(int)

where D = decimal equivalent of the binary code that is loaded

to the DAC register;

0 - 4095 for AD5628 (12 bit)

0 - 16383 for AD5648 (14 bit)

0 - 65535 for AD5668 (16 bit)

N = the DAC resolution

Figure 23. Resistor String

Resistor String

The resistor string section is shown in Figure 23. It is simply a

string of resistors, each of value R. The code loaded to the DAC

tapped off to be fed into the output amplifier. The voltage is

tapped off by closing one of the switches connecting the string

to the amplifier. Because it is a string of resistors, it is

guaranteed monotonic.

Output Amplifier

The output buffer amplifier is capable of generating rail-to-rail

voltages on its output which gives an output range of 0 V to

VDD. It is capable of driving a load of 2 kΩ in parallel with 1000

pF to GND. The source and sink capabilities of the output

amplifier can be seen in Figure 10 and Figure 11. The slew rate

is 1.5 V/µs with a half-scale settling time of 8 µs with the output

unloaded.

SERIAL INTERFACE

The AD5628/AD5648/AD5668 has a three-wire serial interface

(SYNC, SCLK and DIN), which is compatible with SPI, QSPI

and MICROWIRE interface standards as well as most DSPs. See

Figure 2 for a timing diagram of a typical write sequence.

The write sequence begins by bringing the SYNC line low. Data

from the DIN line is clocked into the 32-bit shift register on the

falling edge of SCLK. The serial clock frequency can be as high

as 50 MHz, making the AD5628/AD5648/AD5668 compatible

with high speed DSPs. On the 32nd falling clock edge, the last

data bit is clocked in and the programmed function is executed

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