AD5628 datasheet(17/24 Pages) AD

17 / 24 page

Preliminary Technical Data

AD5628/AD5648/AD5668

Rev. PrA| Page 17 of 24

(i.e., a change in DAC register contents and/or a change in the

mode of operation). At this stage, the SYNC line may be kept

low or be brought high. In either case, it must be brought high

for a minimum of 50 ns before the next write sequence so that a

falling edge of SYNC can initiate the next write sequence. Since

the SYNC buffer draws more current when VIN = 2V than it

does when VIN = 0.8 V, SYNC should be idled low between

write sequences for even lower power operation of the part. As

is mentioned above, however, it must be brought high again just

before the next write sequence.

Input Shift Register

The input shift register is 32 bits wide (see Figure 24). The first

four bits are “don’t cares.” The next four bits are the Command

bits C3-C0, (see Table 1) followed by the 4-bit DAC address

A3-A0, (see Table 2) and finally the 16/14/12-bit data word.

The data word comprises the 16- 14- 12- bit input code

followed by 4, 6 or 8 don’t care bits, the AD5668, AD5648 and

AD5628 respectively. See figure 24, 25, 26. These data bits are

transferred to the DAC register on the 32nd falling edge of

SCLK.

ADDRESS BITS

COMMAND BITS

D15

D14

D13

D12

D11

D10

DB0 (LSB)

Figure 24 AD5668. Input Register Contents

ADDRESS BITS

COMMAND BITS

D13

D12

D11

D10

DB0 (LSB)

Figure 25. AD5648. Input Register Contents

ADDRESS BITS

COMMAND BITS

D11

D10

DB0 (LSB)

Figure 26. AD5628 Input Register Contents

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