AD5628/AD5648/AD5668

Preliminary Technical Data

Rev.PrA | Page 18 of 24

Table 1. Command Definition

Table2. Address Command

SYNC Interrupt

In a normal write sequence, the SYNC line is kept low for 32 falling edges of SCLK and the DAC is updated on the 32nd falling edge and

rising edge of SYNC . However, if SYNC is brought high before the 32nd falling edge this acts as an interrupt to the write sequence. The

shift register is reset and the write sequence is seen as invalid. Neither an update of the DAC register contents or a change in the operating

mode occurs—see Figure 27.

DB31

DB0

SCLK

SYNC

DIN

DB31

DB0

VALID WRITE SEQUENCE, OUTPUT UPDATES

INVALID WRITE SEQUENCE:

SYNC HIGH BEFORE 32ND FALLING EDGE

ON THE 32ND FALLING EDGE

Figure 27. SYNC Interrupt Facility

Command

C3

C2

C1

C0

0

0

0

0

Write to Input Register n

0

0

0

1

Update DAC Register n

0

0

1

0

Write to Input Register n,

Update All

0

0

1

1

Write to and Update DAC

channel n

0

1

0

0

Power Down DAC

(Power-up)

0

1

0

1

Load Clear Code Register

0

1

1

0

Load LDAC Register

(LDAC overwrite)

0

1

1

1

Reset (Power-on-Reset)

1

0

0

0

REF Setup Register

1

0

0

1

Reserved

*

*

*

*

Reserved

1

1

1

1

Reserved

ADDRESS (n)

A3

A2

A1

A0

0

0

0

0

DAC A

0

0

0

1

DAC B

0

0

1

0

DAC C

0

0

1

1

DAC D

0

1

0

0

DAC E

0

1

0

1

DAC F

0

1

1

0

DAC G

0

1

1

1

DAC H

1

1

1

1

All DACs