AD5628 datasheet(9/24 Pages) AD

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Preliminary Technical Data

AD5628/AD5648/AD5668

Rev. PrA| Page 9 of 24

TIMING CHARACTERISTICS

All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

See Figure 2.

(VDD = +2.7 V to +5.5 V; all specifications TMIN to TMAX unless otherwise noted)

Limit at TMIN, TMAX

Parameter

VDD = 2.7 V to 3.6 V

VDD= 3.6 V to 5.5 V

Unit

Conditions/Comments

t1 1

ns min

SCLK Cycle Time

ns min

SCLK High Time

ns min

SCLK Low Time

ns min

SYNC to SCLK Falling Edge Setup Time

ns min

Data Setup Time

ns min

Data Hold Time

ns min

SCLK Falling Edge to SYNC Rising Edge

ns min

Minimum SYNC High Time

ns min

SYNC Rising Edge to SCLK Fall Ignore

t10

ns min

SCLK Falling Edge to SYNC Fall Ignore

t11

ns min

LDAC Pulsewidth Low

t12

ns min

SCLK Falling Edge to LDAC Rising Edge

t13

ns min

/CLR Pulse Width Low

t14

ns min

SCLK Falling Edge to LDAC Falling Edge

t15

tbd

ns min

/CLR Pulse Activation Time (AD5380?)

SCLK

SYNC

DIN

DB31

DB0

t10

t11

t12

LDAC1

LDAC2

t14

NOTES

1. ASYNCHRONOUS LDAC UPDATE MODE.

2. SYNCHRONOUS LDAC UPDATE MODE.

t13

CLR

Figure 2. Serial Write Operation

1 3Maximum SCLK frequency is 50 MHz at VDD = +2.7 V to +5.5 V

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