AD009-041

Page 4 of 14

Version 1.0

Output Sink Current

IOL2

VDD=3V , VOL=0.3V

REM PIN

-

210

-

mA

Input Resistor

Rup

Pull up 150K ohm

-

150

-

K ohm

LVR

VLVR

1.5

V

AC CHARACTERISTICS ( TA = 25℃, VDD = 3V, unless otherwise noted )

LIMIT

PARAMETER

SYMBOL

TEST CONDITIONS

Min

Typ

Max

UNIT

Internal

HRCOSC

Frequency

FOSC2

VDD=1.8V~3.6V

Temp.= -20 ºC ~70 ºC

7.84

8±2%

8.16

MHz

MCU

Operation

frequency

FMCK

VDD=1.8V~3.6V

Use HRCOSC

2

MHz

MCU

Operation

voltage

VOP

1.8

3.0

3.6

V

Internal

LRCOSC

Frequency

FLOSC

VDD=3V

13KHz±50%

KHz

Stable clock delay

after power on or

system reset

CKstable1

( Note 1 )

-

320us +

1024 x (1/ FMCK)

( Note 2 )

us

Stable clock delay

after wake up

CKstable2

System oscillator --HRCOSC

( Note 3 )

-

64 x (1/ FMCK)

( Note 2 )

us

Note1: The stable clock delay ( CKstable 1 ) is place after first clock output of HRCOSC before user’s first

instruction, it means the user’s program will get more stable clock after power on reset.

Note2: FMCK = MCU operating clock

Note3: The stable clock delay ( CKstable 2 ) is place after first clock output of HRCOSC before user’s first

instruction, it means the user’s program will get more stable clock after wake up.

5. FUNCTIONAL DESCRIPTION

5.1 Pro g r am R O M (PR O M)

AD009-041 support two kind of OTP ROM arrangement. The OTP ROM memory plan is shown below:

Address

AD009-041

( 2 K OTP ROM )

000h ~ 0FFh

100h ~ 1FFh

200h ~ 2FFh

…….

500h ~ 5FFh

600h ~ 7DFh

User area 2K

( 2016 X12 )

7E0h ~ 7FFh

Reserved area

Note: 1. The content of OTP ROM address $000h~$7DFh can be read by program. Address

$7E0h~$7FFh can’t be read by program.

2. To read registers DMDL, DMDM and DMDH, only LD A,(n) instruction can be used. Other

instructions are not allowed. ( n= DMDL, DMDM or DMDH )

AD009-041 supports 2 K words OTP ROM which is located on $000h ~ $7DFh, it’s used to stores user

program. The reserved area is $7E0h ~ $7FFh, they can’t be read by program.