AD009-041

Page 12 of 14

Version 1.0

7. Instruction table

affect Z

affect C

JMP Adr

-

-

jump to Adr

JC Adr

-

-

if carry=1 JMP Adr

JNC Adr

-

-

if carry=0 JMP Adr

JZ Adr

-

-

if zero=1 JMP Adr

JNZ Adr

-

-

if zero=0 JMP Adr

CALL Adr

-

-

store return address and JMP Adr

RETS

-

-

return from subroutine

LDPCH Adr

-

-

load PCDH (high address)

LDMAH #D

-

-

load MAH data

LD ExIO(n),A

-

-

Store A to Extend IO

LD A,#D

Y

-

D -> A

LD (n),A

-

-

A -> (n)

LD A,(n)

Y

-

(n) -> A

ADC A,#D

Y

Y

A + D + C -> A

ADC A,(n)

Y

Y

A + (n) + C -> A

SBC A,#D

Y

Y

A - D - C -> A

SBC A,(n)

Y

Y

A - (n) - C -> A

CMP A,#D

Y

Y

A - D

CMP A,(n)

Y

Y

A - (n)

DEC (n)

Y

Y

(n) = (n) - 1

INC (n)

Y

Y

(n) = (n) + 1

ADR (n)

Y

Y

(n) = (n) + C

OR A,#D

Y

-

A = A or D

OR A,(n)

Y

-

A = A or (n)

AND A,#D

Y

-

A = A and D

AND A,(n)

Y

-

A = A and (n)

XOR A,#D

Y

-

A = A xor D

XOR A,(n)

Y

-

A = A xor (n)

RLC (n)

Y

Y

C <- (n) <- C, Z affected by result

RRC (n)

Y

Y

C -> (n) -> C, Z affected by result

SET #B,(m)

Y

-

Set (m)’s #B bit to 1, m= 0 ~ F, B = 0 ~ 3

CLR #B,(m)

Y

-

Clear (m)’s #B bit to 0, m= 0 ~ F, B = 0 ~ 3

NOP

-

-

no operation with 1 cycle length instruction

NOP15

-

-

no operation with 1.5 cycle length instruction

HALT

-

-

stop clock oscillation,

reset watch dog timer(if exists)

CLR C

-

0

C = 0

SET C

-

1

C = 1

CLR Z

0

-

Z = 0

SET Z

1

-

Z = 1

Adr = address

n = register address, 6 bits --- Notice 2

D = data (4 bit)

A = accumulator

Notice 1: Any instruction using “n” isn’t provided for register DMDL, DMDM and DMDH, but only

LD A,(DMDL) , LD A,(DMDM) and LD A,(DMDH) are valid.