AD009-041

Page 5 of 14

Version 1.0

To read OTP ROM valid data, use DMA2~DMA0 registers as address pointer. After these registers

(DMA0~2) are specified by software, the 12bits data of ROM can be moved to A register by three

instructions, they are “LD A, (DMDL)”, “LD A, (DMDM)” and “LD A, (DMDH)”. The three instructions

mentioned above are two cycle instruction, all others instructions are single cycle instruction.

Symbol

Addr

R/W

Reset

D3

D2

D1

D0

Description

DMA0

18H

R/W

xxxx

DMA0.3

DMA0.2

DMA0.1

DMA0.0

DMA1

19H

R/W

xxxx

DMA1.3

DMA1.2

DMA1.1

DMA1.0

DMA2

1AH

R/W

xxxx

DMA2.3

DMA2.2

DMA2.1

DMA2.0

DMA0~DMA2 three registers built a 11 bit

addressing space (DMA2.3 not including)

for read PROM data, DMA0 is lowest

nibble address, DMA2 is highest nibble

address.

DMA2.3: It’s a register only, but for PROM

address setting is useless.

DMDL

1CH

R

xxxx

DMDL.3

DMDL.2

DMDL.1

DMDL.0 DMDL is used to read low nibble data of

PROM by address DMA0~ DMA2.

DMDM

1DH

R/W

xxxx

DMDM.3 DMDM.2 DMDM.1 DMDM.0 DMDM is used to read middle nibble data

of PROM by address DMA0 ~ DMA2.

Writing this register with data 05h will

clear watch dog timer (WDT)

DMDH

1EH

R

xxxx

DMDH.3 DMDH.2 DMDH.1 DMDH.0 DMDH is used to read the high nibble data

PROM by address DMA0~DMA2

For example, assume the data of address 156H is 587H.

LD A, #1

LD (DMA2), A

LD A, #5

LD (DMA1), A

LD A, #6

LD (DMA0), A

; ROM address = 156H

LD A, (DMDL)

; A register = 7H ; low nibble data of ROM address 156H

LD A, (DMDM) ; A register = 8H; middle nibble data of ROM address 156H

LD A, (DMDH) ; A register = 5H; high nibble data of ROM address 156H

5.2 SRA M and I/O Me mo r y Map

AD009-041 series provided 32 nibbles SRAM on the locations $20H~$3FH, these address of SRAM is

different from PROM’s address.

Direct Addressing (use MAH )

Real SRAM Address

SRAM MAP

MAH=XH

( MAH no effect )

00H~1FH

Common I/O port and SFR(special function

register) register

MAH=0H

20H~3FH

00H~1FH

USER SRAM (32x4)

5.2.1 I/O Memory Map

The I/O memory map consists of common I/O and extended I/O. These I/O provide some data operation

instructions as the following:

5. 2. 2 Com m o n I/O

The previously described common block is defined as the common I/O block. A common I/O provided

LD/ADC/SBC/OR/AND/XOR/INC/DEC/RLC/RRC/CMP/ADR operation. SET, CLR ( bit set/clear ) can only be

operated on the address range from 00H to 0FH.