AD009-041

Page 8 of 14

Version 1.0

procedure because reset is first priority when in HALT mode, so program counter will be changed from

$004h to $000h, program counter goes to next address after stable time delay ( CKstable1, see page 5 ).

Furthermore, the SRAM will keep their previous data without changed in this mode.

5.4 Wa tch Dog Ti mer Reset (WDT)

The watch dog timer (WDT) is used to reset whole chip when detect unexpected execution sequence caused

by accident condition, avoiding dead lock of MCU program. This timer can be enabled or disabled by option.

WDT will not have any action when WDT disabled. Software shall run an "clear watch dog timer" (write data

5h to register $1D ) instruction before WDT time out if WDT is enabled. Hardware will generate a reset signal

to reset whole system when WDT overflow. The watch dog timer is a simple counter. The WDT time-out

period is fixed to 0.262±2% Sec.. WDT can works in NORMAL mode but disabled in HALT mode because

the clock source come from internal HRCOSC oscillator.

WDT will be reset when wake up from halt, after power on reset or cleared by software. The reset watch dog

timer sequence is as below :

LD

A, #05H

LD

(1DH), A

; clear watch dog timer

Note 1. For avoiding dead lock and system stable, It’s strongly recommended don’t use more than

one "reset watch dog" in program.

5.5 Programable 8 bi ts TIM E R1

The Timer 1 is an 8 bit up timer. The overflow

interval can be easy generated by reading the

content value of timer 1 and reset values of Timer

1 to 00h by setting TIM1EN=0. The content value

of Timer 1 would be readable only by programmer.

The interrupt isn’t provided in AD009-041 series,

using polling TM1FG is only way to check out the

overflow of Timer1

Symbol

Addr

R/W

Reset D3

D2

D1

D0

Description

TIM1_L

11H

R

0000

TIM1.3

TIM1.2

TIM1.1

TIM1.0

TIM1.3~TIM1.0: Low nibble data of

TIMER 1, it must be read by following

sequence, low nibble first, and then

read high nibble later.

TIM1_H

12H

R

0000

TIM1.7

TIM1.6

TIM1.5

TIM1.4

TIM1.7~TIM1.4: High nibble data of

TIMER 1, it must be read by following

sequence, low nibble first, and then

read high nibble later.

SCALER1

0EH

R/W

0000

TM1EN

TM1FG

T1DIV1

T1DIV0

T1DIV1~T1DIV0: The pre-scaler of

TIMER1

Timer 1 clock source defined below:

FMCK = MCU operating clock

T1DIV1

T1DIV0

TM1CK

0

0

FMCK/8192

0

1

FMCK /4096

1

0

FMCK /2048

1

1

FMCK /1024

TM1FG: Timer 1 overflow flag

0: no overflow occurred.

1: overflow occurred, it can be

cleared by software.

TM1EN: Timer 1 enabled/disabled

0:Timer 1 disabled, the content of

Timer1 is cleared to all 00h.

1:Timer 1 enabled

8 bit Timer 1

Read data

buffer

TM1EN

Overflow

Data bus

Read by

MCU

Resetb

TM1IFG

8

4

FMCK

T1DIV1,T1DIV0