AD009-041

Page 7 of 14

Version 1.0

DMA1

19H

R/W

xxxx

DMA1.3

DMA1.2

DMA1.1

DMA1.0

DMA2

1AH

R/W

xxxx

DMA2.3

DMA2.2

DMA2.1

DMA2.0

bits addressing space (DMA2.3 not

including) for read PROM data, DMA0 is

lowest nibble address, DMA2 is highest

nibble address.

DMA2.3: It’s a register only, but for PROM

address setting is useless.

Reserved

1BH

x

xxxx

X

X

X

X

Reserved

DMDL

1CH

R

xxxx

DMDL.3

DMDL.2

DMDL.1

DMDL.0 DMDL is used to read low nibble data of

PROM by address DMA0~ DMA2.

DMDM

1DH

R/W

xxxx

DMDM.3 DMDM.2 DMDM.1 DMDM.0 DMDM is used to read middle nibble data

of PROM by address DMA0 ~ DMA2.

Writing this register with data 05h will

clear watch dog timer (WDT)

DMDH

1EH

R

xxxx

DMDH.3 DMDH.2 DMDH.1 DMDH.0 DMDH is used to read the high nibble data

PROM by address DMA0~DMA2

Reserved

1FH

R/W

xxxx

X

X

X

X

Reserved

SRAM

32 nibbles

20H~

3FH

R/W

xxxx

SRAM.3

SRAM.2 SRAM.1 SRAM.0

5.2 . 3 Extended I/O

To extend I/O memory space, AD009-041 series provided one special instructions, “LD EXIO(n), A”, where

n = 00H ~ 0FH” to obtain the 16 extra I/O registers. These registers are used for the I/O port pull up

resistors control and wake up control, they can be accessed by two “LD” data transfer instruction only.

For example, the pull up resistor of port A is enabled, the program as shown below.

LD A, #FH

LD EXIO(00H), A

U: unchanged X: unknown value

R/W: readable & writeable R: readable only W: writeable only

Symbol

Addr

R/W

Reset

D3

D2

D1

D0

Description

PAPU

00H

W

0000

PAPU.3

PAPU.2

PAPU.1

PAPU.0

Port A pull up 150K ohm resistor

0: Port A pull up resistor disabled

1: Port A pull up resistor enabled

Reserved

01H

X

xxxx

X

X

X

X

Reserved

PBPU

02H

W

0000

PBPU.3

PBPU.2

PBPU.1

PBPU.0

Port B pull up 150K ohm resistor

0: Port B pull up resistor disabled

1: Port B pull up resistor enabled

Reserved

03H

X

xxxx

X

X

X

X

Reserved

PDPU

04H

W

0000

X

PDPU.2

PDPU.1

PDPU.0

Port D pull up 150K ohm resistor

0: Port D pull up resistor disabled

1: Port D pull up resistor enabled

Reserved

05H

X

xxxx

X

X

X

X

Reserved

PAWK

06H

W

0000

PAWK.3 PAWK.2 PAWK.1 PAWK.0 Port A wake up enable control

0: Port A wake up disabled

1: Port A wake up enabled

PBWK

07H

W

0000

PBWK.3 PBWK.2 PBWK.1 PBWK.0 Port B wake up enable control

0: Port B wake up disabled

1: Port B wake up enabled

PDWK

08H

W

0000

X

PDWK.2 PDWK.1 PDWK.0 Port D wake up enable control

0: Port D wake up disabled

1: Port D wake up enabled

Reserved

09H~

0FH

Reserved

5.3 Ha lt Mode & Wake up

The MCU is changed into HALT mode ( MCU clock and HRCOSC stop) when HALT instruction executed. It

provides a power saving mode for those applications requiring a very low stand-by current. The PA0~PA3,

PB0~PB3 and PD0~PD2 are provided the wake up function when rising edge or falling edge trigger

occurred in halt mode. The program counter will be changed to $004H when HALT instruction executed

immediately, and program counter will go to next address after stable time delay (CKstable3, see page 5 )

while wake up condition occurred. “system resetb” signal will release HALT state and execute reset