AD009-041

Page 9 of 14

Version 1.0

The clock source of Timer 1 can come from the frequency divider, there are 4 kinds of clock rate selected by

register T1DIV1 and T1DIV0 in this divider, and the divider’s clock source is come from MCU operation

clock.

TM1CK= Timer 1 clock source (FMCK = MCU operating clock)

The 8 bits content of Timer 1 can be reset to 00h by TMI1EN setting to 0, it

will be up count while Timer 1 clock source is rising after TIM1EN setting to

1. The read operation sequence of TIM1.7~TIM1.0 must be follow low nibble

(TIM1_L) first and high nibble (TIM1_H) later. The Timer 1 will issue an

overflow flag ( register TM1FG=1 ) when the content data of Timer 1 from

FEh to FFh occurred, and Timer 1 will continue counting from FFh, 00h, 01h… to FFh periodical repeat

automatically.

5.6 Reset

The “system resetb” signal is combine with three signals, they are

power on reset, low voltage reset (LVR) and WDT overflow reset.

The MCU will go back to NORMAL mode when “system resetb”

occurred in HALT mode.

5.7 Lo w Vo ltage Reset

When VDD power is applied to the chip, the low voltage reset circuit default is enabled initially, it will be

disabled when in halt mode. The internal “system resetb” will be generated if VDD power below about

VLVR(1.55V).

5.8 Sy stem C l oc k O s ci ll at o r

The AD009-041 is provided an internal high speed RC oscillator (HRCOSC), 8MHz ±2%. The operating

frequency of AD009-041 is 2 MHz. System clock can be stopped by HALT command. Once stopped, there

are three kinds of signal can re-start oscillation, they are wake-up triggering inputs ( PA0~PA3, PB0~PB3 or

PD0~PD2 ). Such oscillation will do 'stable check' before release control to software. There are some stable

clock delay definition shown on table of page 5, It’s arrange after first clock output of HRCOSC and before

user’s first instruction, it means the user’s program will get more stable clock after power on reset or wake up

from halt mode.

5.9 I/O Port

This chip provided total 10 I/O ports, they are bi-direction I/O port PA0~PA2, PB0~PB3 and PD0~PD2, the

I/O ports provided with input and output direction controlled by IOC_PA, IOC_PB, and IOC_PD, and all I/O

also provided wake up and pull up resistor function by control register.

5. 9. 1 Por t A / P o r t B ( i n put/o ut put)

The Port A, Port B, Port D can be wake up if wake up function are enabled, if I/O port set as output mode,

I/O port direction will be force to input mode automatically by hardware while in halt mode, and IOC_PA,

IOC_PB, IOC_PD are unchanged.

The Port A, Port B, Port D can be wake up by following step:

(1) I/O port wake up and pull high enabled.

(2) (a) I/O port set as output port, and output data is high. (b) or I/O port set as input port.

(3) Delay more than about 200us for I/O stable.

(4) Execution HALT instruction.

(5) MCU will be wake up by I/O port falling or rising edge

Notice: In step (2)-(a) shown above, if set I/O port output low ( not high ) will cause auto wakeup

occurred from halt mode, it seems never sleep. So it’s recommend don’t use set output data low for

wake up condition.

T1DIV1

T1DIV0

TM1CK

0

0

FMCK /8192

0

1

FMCK /4096

1

0

FMCK /2048

1

1

FMCK /1024

WDT

LVR

Power on

reset ckt.

SYSTEM

RESETB