F1978 Datasheet

© 2017 Integrated Device Technology, Inc.

3

Rev O August 28, 2017

Pin Descriptions

Table 1.

Pin Descriptions

Number

Name

Description

1

D5

16dB attenuation control bit. This pin is activated by logic HIGH (see Table 12). [a]

2

RF1

Device RF input or output (bi-directional).

3

DATA

Serial interface data input.

4

CLK

Serial interface clock input.

5

LE

Serial interface latch enable input. Internal pull-up (100kΩ). See “Programming” section for proper

usage of this line.

6

VDD

Power supply pin.

7–9, 12, 18

NC

No internal connection. The NC pins can be left unconnected, have a voltage applied, or be connected

to ground (recommended).

10, 11

GND

Internally grounded. Connect pin directly to paddle ground or as close as possible to the pin with thru

vias.

13

VMODE

Pull this pin HIGH for Serial Control Mode. Ground this pin for Parallel Control Mode.

14

RF2

Device RF input or output (bi-directional).

15

D4

8dB attenuation control bit. This pin is activated by logic HIGH (see Table 12).[a]

16

D3

4dB attenuation control bit. This pin is activated by logic HIGH (see Table 12).[a]

17

D2

2dB attenuation control bit. This pin is activated by logic HIGH (see Table 12).[a]

19

D1

1dB attenuation control bit. This pin is activated by logic HIGH (see Table 12).[a]

20

D0

0.5dB attenuation control bit. This pin is activated by logic HIGH (see Table 12).[a]

EPAD

Exposed paddle. Internally connected to ground (GND). Solder this exposed paddle to a printed circuit

board (PCB) pad that uses multiple ground vias to provide heat transfer out of the device into the PCB

ground planes. These multiple ground vias are also required to achieve the specified RF performance.

[a] There is a 100kΩ pull-up resistor to the internally regulated 2.5V power supply.