F1978 Datasheet

© 2017 Integrated Device Technology, Inc.

16

Rev O August 28, 2017

Figure 20. Latched Parallel Mode Timing Diagram

Table 13. Latched Parallel Mode Timing

Interval Symbol

Description

Min Spec

Max Spec

Units

tSPS

Serial Mode to Parallel Mode setup time

100

ns

tPDH

Parallel data hold time

10

ns

tPDS

LE minimum pulse width

10

ns

tLE

Parallel data setup time

10

ns

Applications Information

F1978 Digital Pin Voltage and Resistance Values (Pins not Connected)

Table 14 lists the resistance between various pins and ground when no DC power is applied. When the device is powered up with +5V DC,

these pins will exhibit a voltage to ground as indicated.

Table 14. Voltage and Resistance to Ground for the Logic Pins

Pin

Name

DC Voltage (Volts)

Resistance (Ohms)

13

VMODE

2.5V

100kΩ pull-up resistor to internally regulated 2.5V.

3, 4, 5

DATA, CLK, LE

2.5V

100kΩ pull-up resistor to internally regulated 2.5V.

1, 15–17,

19, 20

D5, D4, D3,

D2, D1, D0

2.5V

100kΩ pull-up resistor to internally regulated 2.5V.

VMODE

tSPS

tLE

tPDH

tPDS

LE

D[5:0]

Time

Data Word Latched

into the Register