DA7210 datasheet(39/119 Pages) RENESAS

39 / 119 page

DA7210

Ultra-low power stereo codec

Datasheet

Revision 3.2

23-Dec-2021

CFR0011-120-00 Rev 5

39 of 118

● OUT1_R_VOL: 0x1f[5:0]

To enable volume balance settings the gain of the headphone buffers can be programmed

independently for both channels by controls HP_L_VOL (addresses 0x21, and HP_R_VOL

(addresses 0x22, Table 75) according to Table 23. The gain steps are 1.5 dB from +15 dB down

to -54 dB, and mute for the steps below -54 dB. Alternatively the channels’ gain settings can be

combined with bit STEREO_TRACK (address 0x23, Table 76) and controlled for both channels with

volume register HP_R_VOL (address 0x22, Table 75).

For smooth volume changes the gain update can be synchronised to audio signal zero-crossings by

enabling HPZX_L_EN and HPZX_R_EN (address 0x24, Table 77). If no zero-crossing is detected

within 2048 sample periods, the gain change is applied unconditionally. The left and right channels

are synchronised independently.

The headphone outputs are supported by DC offset compensation circuitry to minimise any possible

pop and click artefacts during power up/down. To ensure sufficient time for the DC compensation

circuitry to operate, a delay of 200 ms must be added after SC_MST_EN (address 0x03, Table 45)

bit is enabled.

8.2.5

Ambient noise suppression

DA7210 supports stereo noise suppression by subtracting inverted noise signals from the AUX1

inputs at the headphone outputs. The noise signal must pass through the input PGA, be inverted and

then mixed with the outputs from the DAC. The signal at the AUX1 inputs for example, can be from

microphones picking up ambient noise at the user’s ears.

This mode is enabled via control NOISE_SUP (address 0x01 CONTROL, Table 43) and then offers a

modified headphones volume control via a combination of three gain stages:

Headphones gain settings > 0 dB

All headphone gains settings > 0 dB will be applied to the headphone PGA, but the equivalent gain

will be synchronously subtracted from the input PGA to equalise the overall net gain in the ambient

noise signal path.

For sufficient range of operation, the starting values of INPGA_L_VOL and INPGA_R_VOL (address

0x0C, must be configured >= 10.5 dB (settings 1010 to 1111) before enabling the noise suppression

mode.

Headphones gain settings <= 0 dB

When DAC is selected to the headphone output any update of the gain less than or equal to 0 dB,

using controls HP_L_VOL/HP_R_VOL (address 0x21, Table 74 and address 0x22, Table 75), will be

implemented instead using the controls DAC_L_GAIN and DAC_R_GAIN (address 0x15, Table 62

and address 0x16, Table 63). If this were not the case then a large signal on AUX1 could cause

clipping at the headphone output.

For the ambient noise signals from the AUX1 path all headphones gain changes <= 0 dB will be

implemented using the settings of AUX1_L_VOL and AUX1_R_VOL (address 0x09, Table 50). To

allow the full minimum headphone volume of -54 dB, these AUX1_L_VOL and AUX1_R_VOL

controls need to be set to >= 6 dB (setting > 110101) before enabling the noise suppression mode.

NOTE – The ALC has to be disabled during noise suppression mode and it is recommended to

enable zero-crossing for gain updates at the headphone amplifier and the AUX1 PGA (see the

ramping for DAC playback. The controls INPGA_L_VOL, INPGA_R_VOL, AUX1_L_VOL,

AUX1_R_VOL, DAC_L_GAIN, and DAC_R_GAIN should not be written to when noise suppression is

enabled.

8.2.6

Digital signal processing engine

The digital signal processing engine includes a configurable audio processor that offers flexible

routing and extensive audio enhancement and effects. Linear phase FIR filters perform the

interpolation and decimation for the required sigma-delta sample rates. Configurable high-pass

DA7210 Datasheet(PDF) 39 Page - Renesas Technology Corp

DA7210 Datasheet(HTML) 39 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL