DA7210 datasheet(65/119 Pages) RENESAS

65 / 119 page

DA7210

Ultra-low power stereo codec

Datasheet

Revision 3.2

23-Dec-2021

CFR0011-120-00 Rev 5

65 of 118

PFD / CP

VCO

÷ (9 + Y[n])

Sigma-Delta

Modulator

98.3 or 90.3 MHz

10 – 20 MHz

MCLK

Digital Clock

12.288 / 11.290 MHz

÷ 2

÷ 4

SRM

Lock

Detect

PLL_DIV

WCLK

DAC & ADC Clock

3.072 / 2.822 MHz

Lock

Y[n]

÷ 2

÷ 4

20 – 40 MHz

MCLK

40 – 80 MHz

MCLK

PLL Bypass

÷ 2

15 MHz

OSC

32.768 kHz

MCLK

32 kHz Master Mode

32 kHz mode

Loop Filter

Figure 43: PLL block diagram

9.2.6

Control interface

The DA7210 is selectable to be either a 2-wire or a 4-wire connection (I2C or SPI compliant). The

default for the serial interface is will be default in 2-wire mode, but can be configured to be in 4-wire

mode after a passive to active transition (default: falling edge) is detected three times on the nCS pin

following the power-on-reset, or after the powerdown pin was released. In 2-wire applications the

nCS pin should be tied permanently to the passive state through a resistor. Data is shifted into or out

from DA7210 under control of the host processor that also provides the serial clock.

DA7210

(slave)

Host

processor

nCS/nSS

VDDIO

Slave device

nCS/nSS

VDDIO

4-wire interface

Host

processor

DA7210

Peripheral

device

Peripheral

device

SDA

SCL

SDA

VDDIO

2-wire interface

nCS

Open

Figure 44: Schematic of a 4-wire and a 2-wire control bus

DA7210 Datasheet(PDF) 65 Page - Renesas Technology Corp

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