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DA7210 Datasheet(PDF) 40 Page - Renesas Technology Corp

Part # DA7210
Description  Ultra-low power stereo codec
PDF  119 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

DA7210 Datasheet(HTML) 40 Page - Renesas Technology Corp

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DA7210
Ultra-low power stereo codec
Datasheet
Revision 3.2
23-Dec-2021
CFR0011-120-00 Rev 5
40 of 118
© 2021 Renesas Electronics
filtering (optionally enabled) removes any signal DC offset (see blocks ‘ADC HP’ and ‘DAC HP’ in
Figure 16) and offers 5-band equalisation during recording and sound playback.
Alternatively it can provide dedicated voice band filtering at samples rates
≤ 16 kHz (see blocks ‘ADC
IIR’ and ‘DAC IIR’ in Figure 16).
An additional general purpose (GP) filter engine offers up to eight second-order biquad filter stages
with configurable 16-bit coefficients, and supports flexible digital audio routing and mixing
arrangements. Figure 16 shows some possible routings (a subset of the available settings) for filter
blocks GP1A to GP2D with the related control registers. Typical use cases with example
configurations are explained in the section 8.3.
DAC L
ADC L
ADC R
DAC R
GP2D
GP2C
GP2A
GP1D
GP1C
GP1A
ADC
IIR L
ADC
HP L
DAC
HP L
DAC
IIR L
ADC
HP R
ADC
IIR R
DAC
IIR R
DAC
HP R
I2S/PCM Left
I2S/PCM Right
+
+
+
+
+
+
GP1B
GP2B
+
+
+
DAI Left Input
DAI Left Output
DAI Right Input
DAI Right Output
Figure 16: Digital signal processing engine (simplified block diagram)
The GP filter sections are implemented using a Direct Form 1 architecture, as shown in Figure 17.
This structure implements the transfer function:
H(z) = a0 + a1 z + a2 z2
1-b1 z - b2 z2
z
-1
z
-1
a1
a0
a2
+
+
z
-1
z
-1
+
b2
b1
+
X(n)
Y(n)
e.g.
GP1A_A0L
GP1A_A0H
0x2D/0x2E
e.g.
GP1A_A1L
GP1A_A1H
0x3D/0x3E
e.g.
GP1A_A2L
GP1A_A2H
0x4D/0x4E
e.g.
GP1A_B1L
GP1A_B1H
0x5D/0x5E
e.g.
GP1A_B2L
GP1A_B2H
0x6D/0x6E
Figure 17: Direct form I implementation of a second order IIR filter
Each of the five coefficients may be configured by the user, for each filter section. The coefficients
are specified as 16-bit two’s-complement numbers, ranging from -2 to +2. Denominator coefficients
must be negated, that is, if b1 is positive then a negative value (-b1) must be programmed, and



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