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DA7210 Datasheet(PDF) 61 Page - Renesas Technology Corp

Part # DA7210
Description  Ultra-low power stereo codec
PDF  119 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

DA7210 Datasheet(HTML) 61 Page - Renesas Technology Corp

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DA7210
Ultra-low power stereo codec
Datasheet
Revision 3.2
23-Dec-2021
CFR0011-120-00 Rev 5
61 of 118
© 2021 Renesas Electronics
Table 36: Non-PLL slave mode and PLL master mode sample rate settings
0x2C[3:0]
Sample rate
0000
Not used
0001
8 kHz
0010
11.025 kHz
0011
12 kHz
0100
Not used
0101
16 kHz
0110
22.05 kHz
0111
24 kHz
1000
Not used
1001
32 kHz
1010
44.1 kHz
1011
48 kHz
1100
Not used
1101
Not used
1110
88.1 kHz
1111
96 kHz
If only analogue paths are required then it is possible to use MCLK = 32.768 kHz for the register
setup. For all other 32.768 kHz modes, the PLL must be enabled for any operation that requires
ADC, DAC or digital filtering.
Figure 41: Non-PLL mode start-up sequence shows a basic start-up up configuration sequence for
non-PLL slave mode.



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