DA7210 datasheet(97/119 Pages) RENESAS

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DA7210

Ultra-low power stereo codec

Datasheet

Revision 3.2

23-Dec-2021

CFR0011-120-00 Rev 5

97 of 118

Table 85: PLL 0x2C

Bit

Mode

Symbol

Description

Reset

R/W

PLL_EN

PLL enable

0 = disable and bypass PLL

1 = enable PLL

R/W

MCLK_SRM_EN

Sample rate tracking

0 = disabled

1 = enabled

R/W

MCLK_DET_EN

automatic detection of sample rate

0 = disabled

1 = enabled

R/W

MCLK_SHAPE_EN

Enable MCLK shaper for low level non TTL signals

0 = disabled

1 = enabled

3:0

R/W

In MCLK_DET mode, the value read from this

rate from the PLL track circuitry. This will be

updated on the positive edge of the DAI clock.

0000 = reserved

0001 = 8 kHz

0010 = 11.025 kHz

0011 = 12 kHz

0100 = reserved

0101 = 16 kHz

0110 = 22.05 kHz

0111 = 24 kHz

1000= reserved

1001 = 32 kHz

1010 = 44.1 kHz

1011 = 48 kHz

1100 = reserved

1101 = reserved

1110 = 88.2 kHz

1111 = 96 kHz

1010

10.4 GP filter engine

Table 86: GP1A A0L 0x2D

Bit

Mode

Symbol

Description

Reset

7:0

GP1A A0L

A0L bit 7:0 of A0 coefficient

00000000

Table 87: GP1A A0H 0x2E

Bit

Mode

Symbol

Description

Reset

7:0

GP1A A0H

A0H bit 15:8 of A0 coefficient

01000000

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