ISL70219ASEHFSLASHPROTO datasheet(20/25 Pages) RENESAS

20 / 25 page

ISL70219ASEH

FN8459 Rev. 2.00

Page 20 of 25

Jun 11, 2018

Applications Information

Functional Description

The ISL70219ASEH is a dual, low noise precision operational

amplifier (op amp). This device is fabricated in a new precision

40V complementary bipolar DI process. A super-beta NPN input

stage with input bias current cancellation provides low input bias

current (180pA typical), low input offset voltage (13µV typical),

low input noise voltage (8nV/√Hz), and low 1/f noise corner

frequency (~8Hz). This amplifier also features a high open-loop

gain (14kV/mV) for excellent CMRR (145dB) and THD+N

performance (0.0005% at 3.5VRMS, 1kHz into 2kΩ). A

complementary bipolar output stage enables high capacitive

load drive without external compensation.

Operating Voltage Range

The device is designed to operate across the 4.5V (±2.25V) to

40V (±20V) voltage range and is fully characterized at 10V (±5V)

and 36V (±18V). The Power Supply Rejection Ratio (PSRR)

typically exceeds 140dB across the full operating voltage range

and 120dB minimum across the -55°C to +125°C temperature

range. The worst case common-mode input voltage range

over-temperature is 2V to each rail. With ±18V supplies,

Common-Mode Rejection Ratio (CMRR) performance is typically

>130dB over-temperature. The minimum CMRR performance

across the -55°C to +125°C temperature range is >120dB for

power supply voltages from ±5V (10V) to ±18V (36V).

Input Performance

The super-beta NPN input pair provides excellent frequency

response while maintaining high input precision. High NPN beta

(>1000) reduces input bias current while maintaining good

frequency response, low input bias current, and low noise. Input

bias cancellation circuits provide additional bias current

reduction to <5nA, and excellent temperature stabilization.

Figures 6 through 8 show the high degree of bias current stability

at ±5V and ±18V supplies that is maintained across the -55°C to

+125°C temperature range. The low bias current TC also

produces very low input offset current TC, which reduces DC

input offset errors in precision, high impedance amplifiers.

The +25°C maximum input offset voltage (VOS) is 85µV at ±18V

supplies. The input offset voltage temperature coefficient (VOSTC)

is a maximum of ±1.0µV/°C. The VOS temperature behavior is

smooth (Figures 3 through 5 on page 9), maintaining constant TC

across the entire temperature range.

Input ESD Diode Protection

The input terminals (IN+ and IN-) have internal ESD protection

diodes to the positive and negative supply rails, series connected

500Ω current limiting resistors, and an anti-parallel diode pair

across the inputs (Figure 65).

The series resistors limit the high feed-through currents that can

occur in pulse applications when the input dV/dt exceeds the

0.5V/µs slew rate of the amplifier. Without the series resistors, the

input can forward-bias the anti-parallel diodes, causing current to

flow to the output and resulting in severe distortion and possible

diode failure.

Figure 36 on page 14 provides an example of distortion free large

signal response using a 4VP-P input pulse with an input rise time of

<1ns. The series resistors enable the input differential voltage to

be equal to the maximum power supply voltage (40V) without

damage.

In applications in which one or both amplifier input terminals are

at risk of exposure to high voltages beyond the power supply

rails, current limiting resistors may be needed at the input

terminal to limit the current through the power supply ESD

diodes to 20mA maximum.

Output Current Limiting

The output current is internally limited to approximately ±45mA

at +25°C and can withstand a short circuit to either rail as long

as the power dissipation limits are not exceeded. This applies to

only one amplifier at a time for the dual op amp. Continuous

operation under these conditions can degrade long term

reliability. Figure 14 on page 10 shows the current limit variation

with temperature.

Output Phase Reversal

Output phase reversal is a change of polarity in the amplifier

transfer function when the input voltage exceeds the supply

voltage. The ISL70219ASEH is immune to output phase reversal,

even when the input voltage is 1V beyond the supplies.

FIGURE 65. INPUT ESD DIODE CURRENT LIMITING - UNITY GAIN

VIN

VOUT

V+

V-

500Ω

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