DLPA2000 datasheet(21/68 Pages) TI

21 / 68 page

6.13 Parallel Interface General Timing Requirements

MIN

MAX

UNIT

ƒclock

PCLK frequency

1.0

155.0

MHz

tp_clkper

PCLK period

50% reference points

6.45

1000

tp_clkjit

PCLK jitter

Max ƒclock

See (1)

tp_wh

PCLK pulse duration high

50% reference points

2.43

tp_wl

PCLK pulse duration low

50% reference points

2.43

tp_su

Setup time – HSYNC_CS, DATAEN_CMD,

PDATA(23:0) valid before the active edge of PCLK

50% reference points

0.9

tp_h

Hold time – HSYNC_CS, DATAEN_CMD,

PDATA(23:0) valid after the active edge of PCLK

50% reference points

0.9

Transition time – all signals

20% to 80% reference

points (rising signal)

80% to 20% reference

points (falling signal)

0.2

2.0

tsetup, 3DR

This is the setup time with respect to VSYNC(2)

50% reference points

1.0

thold, 3DR

This is the hold time with respect VSYNC(3)

50% reference points

1.0

(1)

Calculate clock jitter (in ns) using this formula: Jitter = [1 / ƒclock – 5.76 ns]. Setup and hold times must be met even with clock jitter.

(2)

In other words, the 3DR signal must change at least 1.0 ms before VSYNC changes.

(3)

In other words, the 3DR signal must not change for at least 1.0 ms after VSYNC changes.

PCLK

tp_su

tp_h

tp_wh

tp_wl

tp_clkper

Figure 6-8. Parallel Interface Pixel Timing

6.14 Flash Interface Timing Requirements

The DLPC34xx flash memory interface consists of a SPI flash serial interface with a programmable clock rate. The

DLPC34x6 can support 1- to 128-Mb flash memories.(2) (3) (4)

MIN

MAX

UNIT

fclock

SPI_CLK frequency

See (1)

1.4

36.0

MHz

tp_clkper

SPI_CLK period

50% reference points

27.8

704

tp_wh

SPI_CLK pulse duration high

50% reference points

352

tp_wl

SPI_CLK pulse duration low

50% reference points

352

Transition time – all signals

20% to 80% reference

points (rising signal)

80% to 20% reference

points (falling signal)

0.2

3.0

tp_su

Setup time – SPI_DIN valid before SPI_CLK falling edge 50% reference points

10.0

tp_h

Hold time – SPI_DIN valid after SPI_CLK falling edge

50% reference points

0.0

tp_clqv

SPI_CLK clock falling edge to output valid time –

SPI_DOUT and SPI_CSZ

50% reference points

1.0

tp_clqx

SPI_CLK clock falling edge output hold time –

SPI_DOUT and SPI_CSZ

50% reference points

–3.0

3.0

(1)

This range include the ±200 ppm of the external oscillator (but no jitter).

www.ti.com

DLPC3436

DLPS156E – JANUARY 2019 – REVISED APRIL 2023

Submit Document Feedback

Product Folder Links: DLPC3436

DLPA2000 Datasheet(PDF) 21 Page - Texas Instruments

DLPA2000 Datasheet(HTML) 21 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

Datasheet Download

Link URL