LM5069 datasheet(10/22 Pages) NSC

10 / 22 page

Functional Description (Continued)

Good (PGD) output pin indicates when the output voltage is

within 1.25V of the system input voltage (V

SYS). Program-

mable under-voltage lock-out (UVLO) and over-voltage lock-

out (OVLO) circuits shut down the LM5069 when the system

input voltage is outside the desired operating range. The

typical configuration of a circuit card with LM5069 hot swap

protection is shown in Figure 2.

Power Up Sequence

The VIN operating range of the LM5069 is +9V to +80V, with

a transient capability to +100V. Referring to the Block Dia-

gram and Figures 1 and 3, as the voltage at VIN initially

increases, the external N-channel MOSFET (Q1) is held off

by an internal 230 mA pull-down current at the GATE pin.

The strong pull-down current at the GATE pin prevents an

inadvertent turn-on as the MOSFET’s gate-to-drain (Miller)

capacitance is charged. Additionally, the TIMER pin is ini-

tially held at ground. When the VIN voltage reaches the

POR

IT threshold (7.6V) the insertion time begins. During the

insertion time, the capacitor at the TIMER pin (C

T) is charged

by a 5.5 µA current source, and Q1 is held off bya2mA

pull-down current at the GATE pin regardless of the VIN

voltage. The insertion time delay allows ringing and tran-

sients at VIN to settle before Q1 can be enabled. The

insertion time ends when the TIMER pin voltage reaches

4.0V. C

T is then quickly discharged by an internal 1.5 mA

pull-down current. After the insertion time, the LM5069 con-

trol circuitry is enabled when VIN reaches the POR

EN thresh-

old (8.8V). The GATE pin then switches on Q1 when V

SYS

exceeds the UVLO threshold (UVLO pin >2.5V). If V

SYS is

above the UVLO threshold at the end of the insertion time,

Q1 switches on at that time. The GATE pin charge pump

sources 16 µA to charge Q1’s gate capacitance. The maxi-

mum gate-to-source voltage of Q1 is limited by an internal

12V zener diode.

As the voltage at the OUT pin increases, the LM5069 moni-

tors the drain current and power dissipation of MOSFET Q1.

In-rush current limiting and/or power limiting circuits actively

control the current delivered to the load. During the in-rush

limiting interval (t2 in Figure 3) an internal 85 µA fault timer

current source charges C

T. If Q1’s power dissipation and the

input current reduce below their respective limiting thresh-

olds before the TIMER pin reaches 4.0V the 85 µA current

source is switched off, and C

T is discharged by the internal

2.5 µA current sink (t3 in Figure 3). The in-rush limiting

interval is complete when the voltage at the OUT pin in-

creases to within 1.25V of the input voltage (V

SYS), and the

PGD pin switches high.

If the TIMER pin voltage reaches 4.0V before in-rush current

limiting or power limiting ceases (during t2), a fault is de-

clared and Q1 is turned off. See the Fault Timer & Restart

section for a complete description of the fault mode.

20197212

FIGURE 2. LM5069 Application

LM5069 Datasheet(PDF) 10 Page - National Semiconductor (TI)

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