LM5069 datasheet(14/22 Pages) NSC

14 / 22 page

Shutdown Control (Continued)

open drain device, as shown in Figure 7. Upon releasing the

UVLO pin the LM5069 switches on the load current with

in-rush current and power limiting.

Power Good Pin

The Power Good indicator pin (PGD) is connected to the

drain of an internal N-channel MOSFET capable of sustain-

ing 80V in the off-state, and transients up to 100V. An

external pull-up resistor is required at PGD to an appropriate

voltage to indicate the status to downstream circuitry. The

off-state voltage at the PGD pin can be higher or lower than

the voltages at VIN and OUT. PGD is switched high when the

voltage from SENSE to OUT (the external MOSFET’s V

DS)

decreases below 1.25V. PGD switches low when the MOS-

FET’s V

DS is increased past 2.5V. If the UVLO pin is taken

below 2.5V, or the OVLO pin taken above 2.5V, to disable

the LM5069, PGD switches low within 10 µs without waiting

for the voltage at OUT to fall 2.5V below the voltage at

SENSE. The PGD output pin is high when the voltage at VIN

is less than 5V.

Application Information

(Refer to Figure 1)

CURRENT LIMIT, R

The LM5069 monitors the current in the external MOSFET

(Q1) by measuring the voltage across the sense resistor

S), connected from VIN to SENSE. The required resistor

value is calculated from:

(1)

where I

LIM is the desired current limit threshold. If the voltage

across R

S reaches 55 mV, the current limit circuit modulates

the gate of Q1 to regulate the current at I

LIM. While the

current limiting circuit is active, the fault timer is active as

described in the Fault Timer & Restart section. For proper

operation, R

S must be no larger than 100 m

Ω.

While the maximum load current in normal operation can be

used to determine the required power rating for resistor R

basing it on the current limit value provides a more reliable

design since the circuit can operate near the current limit

threshold continuously. The resistor’s surge capability must

also be considered since the circuit breaker threshold is

twice the current limit threshold. Connections from R

S to the

LM5069 should be made using Kelvin techniques. In the

suggested layout of Figure 8 the small pads at the lower

corners of the sense resistor connect only to the sense

resistor terminals, and not to the traces carrying the high

current. With this technique, only the voltage across the

sense resistor is applied to VIN and SENSE, eliminating the

voltage drop across the high current solder connections.

POWER LIMIT THRESHOLD

The LM5069 determines the power dissipation in the exter-

nal MOSFET (Q1) by monitoring the drain current (the cur-

rent in R

S), and the VDS of Q1 (SENSE to OUT pins). The

resistor at the PWR pin (R

PWR) sets the maximum power

dissipation for Q1, and is calculated from the following equa-

tion:

PWR =1.25x10

5 xR

S xPFET(LIM)

(2)

where P

FET(LIM) is the desired power limit threshold for Q1,

and R

S is the current sense resistor described in the Current

20197217

FIGURE 7. Shutdown Control

20197219

FIGURE 8. Sense Resistor Connections

LM5069 Datasheet(PDF) 14 Page - National Semiconductor (TI)

LM5069 Datasheet(HTML) 14 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

Datasheet Download

Link URL