LM5069 datasheet(15/22 Pages) NSC

15 / 22 page

Application Information

(Refer to Figure 1) (Continued)

Limit section. For example, if R

S is 10 m

Ω , and the desired

power limit threshold is 60W, R

PWR calculates to 75 k

Ω.If

Q1’s power dissipation reaches the threshold Q1’s gate is

modulated to reduce the load current, keeping Q1’s power

from exceeding the threshold. For proper operation of the

power limiting feature, R

PWR must be

≤150 kΩ. While the

power limiting circuit is active, the fault timer is active as

described in the Fault Timer & Restart section. Typically,

power limit is reached during startup, or if the output voltage

falls due to a severe overload or short circuit.

The programmed maximum power dissipation should have a

reasonable margin from the maximum power defined by the

FET’s SOA chart if the LM5069-2 is used since the FET will

be repeatedly stressed during fault restart cycles. The FET

manufacturer should be consulted for guidelines.

If the application does not require use of the power limit

function the PWR pin can be left open.

TURN-ON TIME

The output turn-on time depends on whether the LM5069

operates in current limit, or in both power limit and current

limit, during turn-on.

A) Turn-on with current limit only: The current limit thresh-

old (I

LIM) is determined by the current sense resistor (RS). If

the current limit threshold is less than the current defined by

the power limit threshold at maximum V

DS the circuit oper-

ates at the current limit threshold only during turn-on. Refer-

ring to Figure 11a, as the load current reaches I

LIM, the

gate-to-source voltage is controlled at V

GSL to maintain the

current at I

LIM. As the output voltage reaches its final value

) 0V) the drain current reduces to its normal operating

value, and the gate is charged to approximately 12V

GATE). The time for the OUT pin voltage to transition from

zero volts to V

SYS is equal to:

where C

L is the load capacitance. For example, if VSYS =

48V, C

L = 1000 µF, and ILIM = 1A, tON calculates to 48 ms.

The maximum instantaneous power dissipated in the MOS-

FET is 48W. This calculation assumes the time from t1 to t2

in Figure 11a is small compared to t

ON, and the load does not

draw any current until after the output voltage has reached

its final value, and PGD switches high (Figure 9). If the load

draws current during the turn-on sequence (Figure 10), the

turn-on time is longer than the above calculation, and is

approximately equal to:

where R

L is the load resistance. The Fault Timeout Period

must be set longer than t

ON to prevent a fault shutdown

before the turn-on sequence is complete.

B) Turn-on with power limit and current limit: The maxi-

mum allowed power dissipation in Q1 (P

FET(LIM)) is defined

by the resistor at the PWR pin, and the current sense resistor

S. See the Power Limit Threshold section. If the current

limit threshold (I

LIM) is higher than the current defined by the

power limit threshold at maximum V

DS (PFET(LIM)/VSYS) the

circuit operates initially at the power limit mode when the

DS of Q1 is high, and then transitions to current limit mode

as the current increases to I

LIM and VDS decreases. See

Figure 11b. Assuming the load (R

L) is not connected during

turn-on, the time for the output voltage to reach its final value

is approximately equal to:

For example, if V

SYS = 48V, CL = 1000 µF, ILIM = 1A, and

FET(LIM) = 20W, tON calculates to

)68 ms, and the initial

current level (I

P) is approximately 0.42A. The Fault Timeout

Period must be set longer than t

ON.

20197222

FIGURE 9. No Load Current During Turn-On

20197223

FIGURE 10. Load Draws Current During Turn-On

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