LM5069 datasheet(16/22 Pages) NSC

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Application Information

(Refer to Figure 1) (Continued)

MOSFET SELECTION

It is recommended that the external MOSFET (Q1) selection

be based on the following criteria:

The BV

DSS rating should be greater than the maximum

system voltage (V

SYS), plus ringing and transients which can

occur at V

SYS when the circuit card, or adjacent cards, are

inserted or removed.

The maximum continuous current rating should be based

on the current limit threshold (55 mV/R

S), not the maximum

load current, since the circuit can operate near the current

limit threshold continuously.

The Pulsed Drain Current spec (I

DM) must be greater

than the current threshold for the circuit breaker function

(105 mV/R

S).

The SOA (Safe Operating Area) chart of the device, and

the thermal properties, should be used to determine the

maximum power dissipation threshold set by the R

PWR re-

sistor. The programmed maximum power dissipation should

have a reasonable margin from the maximum power defined

by the FET’s SOA chart if the LM5069-2 is used since the

FET will be repeatedly stressed during fault restart cycles.

The FET manufacturer should be consulted for guidelines.

-R

DS(on) should be sufficiently low that the power dissipa-

tion at maximum load current (I

L(max)

2 xR

DS(on)) does not

raise its junction temperature above the manufacturer’s rec-

ommendation.

If the device chosen for Q1 has a maximum V

GS rating less

than 12V, an external zener diode must be added from its

gate to source, with the zener voltage less than the maxi-

mum V

GS rating. The zener diode’s forward current rating

must be at least 250 mA to conduct the GATE pull-down

current during startup and in the circuit breaker mode.

TIMER CAPACITOR, C

The TIMER pin capacitor (C

T) sets the timing for the inser-

tion time delay, fault timeout period, and restart timing of the

LM5069-2.

A) Insertion Delay - Upon applying the system voltage

SYS) to the circuit, the external MOSFET (Q1) is held off

during the insertion time (t1 in Figure 3) to allow ringing and

transients at V

SYS to settle. Since each backplane’s re-

sponse to a circuit card plug-in is unique, the worst case

settling time must be determined for each application. The

insertion time starts when VIN reaches the POR

IT threshold,

at which time the internal 5.5 µA current source charges C

from 0V to 4.0V. The required capacitor value is calculated

from:

For example, if the desired insertion delay is 250 ms, C

calculates to 0.345 µF. At the end of the insertion delay, C

T is

quickly discharged by a 1.5 mA current sink.

B) Fault Timeout Period - During in-rush current limiting or

upon detection of a fault condition where the current limit

and/or power limit circuits regulate the current through Q1,

the fault timer current source (85 µA) is switched on to

charge C

T. The Fault Timeout Period is the time required for

the TIMER pin voltage to reach 4.0V, at which time Q1 is

switched off. The required capacitor value for the desired

Fault Timeout Period t

FAULT is calculated from:

(3)

For example, if the desired Fault Timeout Period is 16 ms,

T calculates to 0.34 µF. After the Fault Timeout Period, the

LM5069-1 latches the GATE pin low until a power up se-

quence is initiated by external circuitry. C

T is discharged by

the 2.5 µA current sink at the end of the Fault Timeout

Period. See the Fault Timer and Restart section and Figure

5. When the Fault Timeout Period of the LM5069-2 expires,

a restart sequence starts as described below (Restart Tim-

ing). Since the LM5069 normally operates in power limit

and/or current limit during a power up sequence, the Fault

Timeout Period must be longer than the time required for the

output voltage to reach its final value. See the Turn-on Time

section.

C) Restart Timing For the LM5069-2, after the Fault Tim-

eout Period described above, C

T is discharged by the 2.5 µA

current sink to 1.25V. The TIMER pin then cycles through

20197225

FIGURE 11. MOSFET Power Up Waveforms

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