TMP1827 datasheet(16/65 Pages) TI

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Table 9-2. Legacy (12-Bit) Temperature Data Format (continued)

TEMPERATURE

(°C)

DIGITAL OUTPUT

BINARY

HEXADECIMAL

–40

1111 1101 1000 0000

FD80

–55

1111 1100 1001 0000

FC90

9.3.5 Temperature Offset

The temperature offset has the same format as the temperature result and is stored in the temperature offset

registers.

The device, after every temperature conversion, applies the offset value before the temperature is stored in the

temperature result register. The host write to the offset register can be stored in the configuration EEPROM of

the device, which removes the overhead for the host to reprogram the value or reapply in software at every

power up. The offset features allow the device to achieve better accuracy at the temperature range for the

application by performing a single point calibration.

9.3.6 Temperature Alert

The temperature alert feature uses the temperature alert low registers for low threshold comparison and

temperature alert high registers for high threshold comparison. The format of the register is the same as the

temperature results.

The device shall compare the result of the last conversion with the alert thresholds. If the temperature result

is less than the low limit, or more than the high limits, then the device shall set the appropriate alert status

flag, in the status register. The alert status flags are cleared based on the ALERT_MODE setting in the device

configuration-1 register.

Additionally, if the IO2/ALERT pin is configured as an alert pin, the alert status is reflected on the pin in supply

powered mode.

9.3.7 Standard Device Address

Every device comes with a unique 64-bit address that is factory programmed. Additionally the device provides

flexible addressing modes that the host controller may use to improve bus throughput. This is described below.

9.3.7.1 Unique 64-Bit Device Address and ID

The device has a hard-coded, 64-bit address which is factory programmed and cannot be altered by the

customer application. The unique 64-bit device address is used for device addressing in the end application and

for NIST traceability. Figure 9-3 shows the format of the 64-bit address. When the host accesses the device or

when the device sends its address, the 64-bit unique address is sent least significant bit first. The unique 64-bit

address consists of 3 fields. The lower 8 bits consists of the device family code, followed by a 48-bit unique

number and 8-bit CRC checksum on the 56 bits preceding it.

The device family code for TMP1827 shall read as 27h.

8-bit Device Family

48-bit Unique Address

8-bit CRC

MSb

LSb

Bit-63

Bit-0

Figure 9-3. 64-Bit Device Address

9.3.8 Flexible Device Address

Depending on the user application case, the TMP1827 provides for some user and application configurable

address modes, called flexible address mode. These modes exist alongside the standard device address, and is

extremely useful for applications that require a combination of faster access and device position identification.

When the flexible device address is used, the short address register is updated. The short address register shall

be updated by the host write when the FLEX_ADDR_MODE bits are '00b'. When these bits are changed from

TMP1827

SBOSA15A – SEPTEMBER 2022 – REVISED MAY 2023

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