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TMP1827 Datasheet(PDF) 27 Page - Texas Instruments

Part # TMP1827
Description  TMP1827 1-Wire®, ±0.2°C Accurate Temperature Sensor With SHA-256-HMAC Authentication Engine, 2Kb EEPROM
PDF  65 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMP1827 Datasheet(HTML) 27 Page - Texas Instruments

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9.4.2.2 Comparator Mode
The device operates in comparator mode, when the ALERT_MODE is set as '1b'. In the alert mode of operation,
the alert status flag and IO2/ALERT pin are asserted when the last temperature conversion is either higher than
the temperature alert high limit or when it is lower than the temperature alert low limit register.
The alert status flag and IO2/ALERT pin are deasserted only when the result of the last temperature conversion
is less than the temperature alert high limit minus the hysteresis or above the temperature low limit plus the
hysteresis as shown in Figure 9-18. The hysteresis is selectable using the HYSTERESIS bit field in the device
configuration-2 register.
ALERT_HIGH
ALERT_LOW
Temperature
Temperature conversions
ALERT_HIGH
ALERT_LOW
Alert Status Read
ALERT pin
ALERT_LOW+HYSTERESIS
ALERT_HIGH-HYSTERESIS
Figure 9-18. Comparator Mode Timing Diagram
9.4.3 1-Wire Interface Communication
To leverage the features effectively, the device access consists of three distinct phases. As shown in Figure
9-19, any bus communication starts with a bus reset condition to which every device on the bus must respond.
This is followed by a highly configurable address phase, where the host selects the device it wants to access.
Finally, there is a function phase where the host provides the selected device(s) the action it wants to take.
Reset
Command
Device Address
Func on
Write Data
Bus Reset Phase
Address Phase
Func on Phase
Answer to
Reset
Read Data
CRC
Figure 9-19. 1-Wire Bus Communication
In a 1-Wire bus, all write and reads are initiated by the host except for the answer to reset which is initiated by
the devices on the bus.
9.4.3.1 Bus Reset Phase
The bus reset phase is the beginning of the communication. The phase is initiated by the host by holding the
1-Wire data line low for a period tRSTL. All devices on the bus, irrespective of their current state shall respond
www.ti.com
TMP1827
SBOSA15A – SEPTEMBER 2022 – REVISED MAY 2023
Copyright © 2023 Texas Instruments Incorporated
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