TMP1827 datasheet(3/65 Pages) TI

3 / 65 page

5 Description (cont.)

The TMP1827 implements the SHA-256-HMAC authentication engine along with key storage, for system

authentication requirements of an end equipment. The 2Kb EEPROM on the device allows the host application

to store application specific content in block sizes of 64-bit. The memory can be write protected in page size

of 256-bits to avoid accidental data overwrite. The memory architecture enables application to optimize the bus

bandwidth when updating variables which are only few bytes while providing an optimal memory size for write

protection. The device also features mechanism for host authentication by means of authenticated memory write

operations.

6 Device Comparison

Table 6-1. Device Comparison

FEATURE

TMP1826

TMP1827

TMP1827N(1)

Best Accuracy

0.2°C

0.9°C

Temperature Range

–55°C to +150°C

Memory Size

2Kb

Memory Write protection

Yes

Authenticated Memory Write

Yes

Authentication type

SHA-256-HMAC

Bus speeds

Standard and Overdrive

Drop in replacement package

NGR (2.5 mm × 2.5 mm, WSON) NGR (2.5 mm × 2.5 mm, WSON) NGR (2.5 mm × 2.5 mm, WSON)

Alternate package

DGK (3.0 mm × 4.9 mm, VSSOP)

(1)

TMP1827N is an orderable option for the TMP1827. See the orderable addendum at the end of the data sheet.

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TMP1827

SBOSA15A – SEPTEMBER 2022 – REVISED MAY 2023

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TMP1827 Datasheet(PDF) 3 Page - Texas Instruments