TMP1827 datasheet(28/65 Pages) TI

28 / 65 page

to the bus reset, by reinitializing their internal state and responding to the host initiated bus reset. The devices

respond after a minimum of tPDH, by holding the 1-Wire low for a time period of tRSTH as shown in Figure 8-1.

All devices when powered up are configured with the OD_EN bit set as '1' in the device configuration-2 and OD

flag set as '1' in status register. If the host sends a bus reset pulse of 48 µs to 80 µs, then only devices operating

in overdrive speed shall respond to the bus reset pulse, while devices operating in standard mode shall continue

to wait for a standard mode bus reset.

If the host sends a bus reset pulse of minimum tRSTL for standard mode, the device shall reset the OD_EN bit

to '0' and respond to the bus reset in standard mode. If the bus consists of mixed standard and overdrive speed

devices, then sending a bus reset pulse in standard mode shall reset all devices to standard mode speed of

operation.

It is illegal for the host to send the bus reset for a particular speed of operation and then communicate at the

other speed mode. Also, if a bus reset pulse is sent which is greater than 80 µs (but less than 480 µs), then the

device communication shall be reset, though the device operation is not ensured.

9.4.3.2 Address Phase

Figure 9-20 shows the address phase that follows the bus reset phase. During this phase, the host presents 8-bit

commands which may be followed by either host sending a 64-bit device address, a 8-bit flexible address, or

skipping the address. Some of the commands are used to discover the device address, while others are used to

select the device.

Host Sends Reset

Pulse

TMP18xx switches

to Standard Speed.

OD Flag = 0

Is Reset pulse

width for Standard

Speed?

TMP18xx Responds

in Overdrive Speed

Host Sends Address

Command

33h (READADDR)?

55h (MATCHADDR)?

F0h (SEARCHADDR)?

CCh (SKIPADDR)?

Yes

TMP18xx Sends 8 Bytes of

Address, LSb to MSb

Host Sends 8 Bytes of

Address, LSb to MSb

Does TMP18xx

Address Match?

Address Search Algorithm

Host Sends Func on

Yes

ECh (ALERTSEARCH)?

TMP18xx with

Alert Flag Set?

Yes

TMP18xx Sends FLAG

Yes

Host Sends FLAG

69h

(OVD_MATCHADDR)?

Host Sends 8 Bytes of

Address, LSb to MSb

Does TMP18xx

Address Match?

Yes

OD Flag = 1

OD Flag = 0

3Ch

(OVD_SKIPADDR)?

Yes

OD Flag = 0

0Fh (FLEXADDR)?

Host Sends 1 Byte of

Short Address, LSb to MSb

Yes

Does TMP18xx Short

Address Match?

Yes

Is device in

Standard Speed?

Yes

Figure 9-20. Address Phase Flowchart

9.4.3.2.1 READADDR (33h)

The command can be used by the host to read the 64-bit address of the device. This command must only be

used when there is one device on the bus, as this command will cause a collision if multiple devices are present

on the bus.

TMP1827

SBOSA15A – SEPTEMBER 2022 – REVISED MAY 2023

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