CS42L52 datasheet(46/82 Pages) CIRRUS

46 / 82 page

DS680A1

CS42L52

6.5.6

MCLK Divide By 2

Divides the input MCLK by 2 prior to all internal circuitry.

Note:

In slave mode, this bit is ignored when the AUTO bit (“Auto-Detect” on page 44) is disabled.

6.6

Interface Control 1 (Address 06h)

6.6.1

Master/Slave Mode

Configures the serial port I/O clocking.

6.6.2

SCLK Polarity

Configures the polarity of the SCLK signal.

6.6.3

ADC Interface Format

Configures the digital interface format for data on SDOUT.

6.6.4

DSP Mode

Configures a data-packed interface format for both the ADC and DAC.

Notes:

1. Select the audio word length using the AWL[1:0] bits (“Audio Word Length” on page 47).

2. The interface format for both the ADC and the DAC must be set to “Left-Justified” when DSP Mode

is enabled.

MCLKDIV2

MCLK signal into CODEC

No divide

Divided by 2

Application:

“Serial Port Clocking” on page 34

543

M/S

INV_SCLK

ADCDIF

DSP

DACDIF1

DACDIF0

AWL1

AWL0

M/S

Serial Port Clocks

Slave (input ONLY)

Master (output ONLY)

INV_SCLK

SCLK Polarity

Not Inverted

Inverted

ADCDIF

ADC Interface Format

Left Justified

1I²S

Application:

“Digital Interface Formats” on page 36

DSP

DSP Mode

Disabled

Enabled

Application:

“DSP Mode” on page 36

CS42L52 Datasheet(PDF) 46 Page - Cirrus Logic

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