CS42L52 datasheet(27/82 Pages) CIRRUS

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DS680A1

CS42L52

4.2.1

MIC Inputs

The input pins 21, 22, 23 and 24 accept stereo line-level or microphone signals. For microphone inputs,

either single-ended or differential configuration is allowed, providing programmable pre-amplification of

low-level signals. In the single-ended configuration, an internal MUX chooses one of two stereo sets (se-

lection is made independently on channels A and B). In the differential configuration, an internal voltage

follower cascaded with the pre-amplifier maintains high input impedance and provides noise rejection

above the MICxGAIN setting. The pre-amps are biased to VQ in both configurations.

4.2.2

Automatic Level Control (ALC)

When enabled, the ALC monitors the analog input signal after the digital attenuator, detects when peak

levels exceed the maximum threshold settings and lowers, first, the PGA gain settings and then increases

the digital attenuation levels at a programmable attack rate and maintains the resulting level below the

maximum threshold.

When input signal levels fall below the minimum threshold, digital attenuation levels are decreased first

and the PGA gain is then increased at a programmable release rate and maintains the resulting level

above the minimum threshold.

Attack and release rates are affected by the ADC soft ramp/zero cross settings and sample rate, Fs. ALC

soft ramp and zero cross dependency may be independently enabled/disabled.

Recommended settings: Best level control may be realized with the fastest attack and slowest release

setting with soft ramp enabled in the control registers.

Notes:

1. When ALC x is enabled and the PGAxVOL[5:0] is set above 12 dB, the ADCxVOL[7:0] should not be

set below 0 dB.

2. The maximum realized gain must be set in the PGAxVOL register. The ALC will only apply the gain

set in the PGAxVOL.

3. The ALC maintains the output signal between the MIN and MAX thresholds. As the input signal level

changes, the level-controlled output may not always be the same but will always fall within the

thresholds.

Referenced Control

MICxCFG ............................

PDN_MICx ..........................

MICxGAIN ...........................

“MICx Configuration” on page 55

“Power Down MICx” on page 43

“MICx Gain” on page 55

Referenced Control Register Location

PGAxVOL[5:0

MAX[2:0], MIN[2:0]

“PGAx Vol. & ALCx Transition Ctl.: ALC, PGA A (Address 12h) & ALC, PGA B (Address 13h)” on page 55

“ALC Threshold (Address 2Ch)” on page 68

MIC1-

MIC1+

MIC2-

MIC2+

MICACFG=’1'b

MICBCFG=’1'b

MICAGAIN[4:0]

MICBGAIN[4:0]

16..32 dB/

1 dB steps

16..32 dB/

1 dB steps

PDN_MICA=’0'b

PDN_MICB=’0'b

to summing

PGA A

Note: Output to PGA = (MIC

+ - MIC-)*gain + MIC-

to summing

PGA B

MIC1A

MIC2A

MIC1B

MIC2B

MICACFG=’0'b

MICBCFG=’0'b

MICAGAIN[4:0]

MICBGAIN[4:0]

16..32 dB/

1 dB steps

16..32 dB/

1 dB steps

PDN_MICA=’0'b

PDN_MICB=’0'b

MICASEL

MICBSEL

to summing

PGA A

to summing

PGA B

Figure 6. Single-Ended MIC Configuration

Figure 7. Differential MIC Configuration

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