CS42L52 datasheet(42/82 Pages) CIRRUS

42 / 82 page

DS680A1

CS42L52

6. REGISTER DESCRIPTION

All registers are read/write except for the chip I.D. and Revision Register and Interrupt Status Register which are

read only. See the following bit definition tables for bit assignment information. The default state of each bit after a

power-up sequence or reset is listed in each bit description. All “Reserved” bits must maintain their default value.

6.1

Chip I.D. and Revision Register (Address 01h) (Read Only)

6.1.1

Chip I.D. (Read Only)

I.D. code for the CS42L52.

6.1.2

Chip Revision (Read Only)

CS42L52 revision level.

6.2

Power Control 1 (Address 02h)

6.2.1

Power Down ADC Charge Pump

Configures the power state of the ADC charge pump.

6.2.2

Power Down PGAx

Configures the power state of PGA channel x.

Notes:

1. The CS42L52 employs a clever scheme for controlling the power to the PGA when PASSTHRU

(“Passthru Analog” on page 52) is enabled. Refer to the referenced application for more information.

2. This bit is also used in conjunction with AINx_SEL bits to determine the analog input path to the ADC.

Refer to “ADC Input Select” on page 48 for the required settings.

543

CHIPID4

CHIPID3

CHIPID2

CHIPID1

CHIPID0

REVID2

REVID1

REVID0

CHIPID[4:0]

Device

11100

CS42L52

REVID[2:0]

Revision Level

000

001

010

543

PDN_CHRG

Reserved

PDN_PGAB

PDN_PGAA

PDN_ADCB

PDN_ADCA

PDN

PDN_CHRG

ADC Charge Pump Status

Powered Up

Powered Down

PDN_PGAx

PGA Status

Powered Up (ONLY when the ADC or the analog passthru is used)

Powered Down

Application

“Analog In to Analog Out Passthru” on page 32

CS42L52 Datasheet(PDF) 42 Page - Cirrus Logic

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