EPCS4 datasheet(13/32 Pages) ALTERA

13 / 32 page

Altera Corporation

Core Version a.b.c variable

4–13

July 2004

Configuration Handbook, Volume 2

Serial Configuration Devices (EPCS1, EPCS4, EPCS16 & EPCS64) Data Sheet

Read Status Operation

The read status operation code is

b'0000 0101, with the MSB listed first.

You can use the read status operation to read the status register.

Figures 4–7 and 4–8 show the status bits in the status register of both

serial configuration devices.

Figure 4–7. EPCS4 Status Register Status Bits

Figure 4–8. EPCS1 Status Register Status Bits

Setting the write in progress bit to 1 indicates that the serial configuration

device is busy with a write or erase cycle. Resetting the write in progress

bit to 0 means no write or erase cycle is in progress.

Resetting the write enable latch bit to

0 indicates that no write or erase

cycle will be accepted. Set the write enable latch bit to

1 before every write

bytes, write status, erase bulk, and erase sector operation.

The non-volatile block protect bits determine the area of the memory

protected from being written or erased unintentionally. Tables 4–9 and

4–10 show the protected area in both serial configuration devices with

reference to the block protect bits. The erase bulk operation is only

Bit 7

Bit 0

Block Protect Bits [2..0]

Write In

Progress Bit

Write Enable

Latch Bit

BP2

BP1

BP0

WEL

WIP

Bit 7

Bit 0

Block Protect

Bits [1..0]

Write In

Progress Bit

Write Enable

Latch Bit

BP1

BP0

WEL

WIP

EPCS4 Datasheet(PDF) 13 Page - Altera Corporation

EPCS4 Datasheet(HTML) 13 Page - Altera Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Datasheet Download

Link URL