EPCS4 datasheet(25/32 Pages) ALTERA

25 / 32 page

Altera Corporation

Core Version a.b.c variable

4–25

July 2004

Configuration Handbook, Volume 2

Serial Configuration Devices (EPCS1, EPCS4, EPCS16 & EPCS64) Data Sheet

Table 4–12 defines the serial configuration device timing parameters for

write operation.

Figure 4–17 shows the timing waveform for the serial configuration

device's read operation.

Table 4–12. Write Operation Parameters

Symbol

Parameter

Min

Max

Unit

fWCLK

Write clock frequency (from

FPGA, download cable, or

embedded processor) for write

enable, write disable, read

status, read silicon ID, write

bytes, erase bulk, and erase

sector operations

MHz

tCH

DCLK high time

tCL

DCLK low time

tNCSSU

Chip select (

nCS) setup time

tNCSH

Chip select (

nCS) hold time

tDSU

Data (

ASDI) in setup time

before rising edge on

DCLK

5ns

tDH

Data (

ASDI) hold time after

rising edge on

DCLK

5ns

tCSH

Chip select high time

100

tWB_EPCS1 (1)

Write bytes cycle time for

EPCS1 devices

tWB_EPCS4 (1)

Write bytes cycle time for

EPCS4 devices

1.5

tWS (1)

Write status cycle time

tEB_EPCS1 (1)

Erase bulk cycle time for

EPCS1 devices

tEB_EPCS4 (1)

Erase bulk cycle time for

EPCS4 devices

510

tES (1)

Erase sector cycle time

Note to Table 4–12:

(1)

These parameters are not shown in Figure 4–16.

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