EPCS4 datasheet(24/32 Pages) ALTERA

24 / 32 page

4–24

Core Version a.b.c variable

Altera Corporation

Configuration Handbook, Volume 2

July 2004

Timing Information

parameter specifies the VCC supply current when the device is in active

power mode and the ICC0 parameter specifies the current when the device

is in stand-by power mode (see Table 4–18).

Power-On Reset

During initial power-up, a POR delay occurs to ensure the system voltage

levels have stabilized. During AS configuration, the FPGA controls the

configuration and has a longer POR delay than the serial configuration

device. Therefore, the POR delay is governed by the Stratix II FPGA

(typically 12 ms or 100 ms) or Cyclone series FPGA (typically 100 ms).

Error Detection

During AS configuration with the serial configuration device, the FPGA

monitors the configuration status through the

nSTATUS and CONF_DONE

pins. If an error condition occurs (

nSTATUS drives low) or if the

CONF_DONE pin does not go high, the FPGA will initiate reconfiguration

by pulsing the

nSTATUS and nCSO signals, which controls the chip select

pin on the serial configuration device (

nCS).

After an error, configuration automatically restarts if the Auto-Restart

Upon Frame Error option is turned on in the Quartus II software. If the

option is turned off, the system must monitor the

nSTATUS signal for

errors and then pulse the

nCONFIG signal low to restart configuration.

Timing

Information

Figure 4–16 shows the timing waveform for write operation to the serial

configuration device.

Figure 4–16. Write Operation Timing

nCS

DCLK

ASDI

DATA

tNCSH

tDSU

tNCSSU

tCH

tCL

tCSH

tDH

Bit n

Bit 0

Bit n

- 1

High Impedance

EPCS4 Datasheet(PDF) 24 Page - Altera Corporation

EPCS4 Datasheet(HTML) 24 Page - Altera Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Datasheet Download

Link URL