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EPCS4 Datasheet(PDF) 18 Page - Altera Corporation |
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EPCS4 Datasheet(HTML) 18 Page - Altera Corporation |
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18 / 32 page ![]() 4–18 Core Version a.b.c variable Altera Corporation Configuration Handbook, Volume 2 July 2004 Serial Configuration Device Memory Access Read Silicon ID Operation The read silicon ID operation code is b'1010 1011, with the MSB listed first. This operation reads the serial configuration device’s 8-bit silicon ID from the DATA output pin. If this operation is shifted in during an erase or write cycle, it will be ignored and have no effect on the cycle that is in progress. Table 4–11 shows the EPCS1 and EPCS4 device silicon IDs. The device implements the read silicon ID operation by driving nCS low then shifting in the read silicon ID operation code followed by three dummy bytes on ASDI. The serial configuration device’s 8-bit silicon ID is then shifted out on the DATA pin on the falling edge of DCLK, as shown in Figure 4–12. The device can terminate the read silicon ID operation by driving nCS high after the silicon ID has been read at least once. Sending additional clock cycles on DCLK while nCS is driven low can cause the silicon ID to be shifted out repeatedly. Table 4–11. Serial Configuration Device Silicon ID Serial Configuration Device Silicon ID (Binary Value) EPCS1 b'0001 0000 EPCS4 b'0001 0010 |
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