EPCS4 datasheet(27/32 Pages) ALTERA

27 / 32 page

Altera Corporation

Core Version a.b.c variable

4–27

July 2004

Configuration Handbook, Volume 2

Serial Configuration Devices (EPCS1, EPCS4, EPCS16 & EPCS64) Data Sheet

Figure 4–18 shows the timing waveform for FPGA AS configuration

scheme using a serial configuration device.

Figure 4–18. AS Configuration Timing

Table 4–14 shows the timing parameters for AS configuration mode.

Read Address

bit

− 1

bit

bit 1

bit 0

tCL

tCH

tSU

136 Cycles

nSTATUS

nCONFIG

CONF_DONE

nCSO

DCLK

ASDO

DATA0

INIT_DONE

User I/O

User Mode

tPOR

Table 4–14. Timing Parameters for AS Configuration

Symbol

Parameter

Min

Typ

Max

Unit

fCLK

DCLK frequency from Cyclone FPGA

MHz

fCLK

DCLK frequency from Stratix II or Cyclone II FPGA

(1)

20 (2)

26 (2)

40 (2)

MHz

tCH

DCLK high time

tCL

DCLK low time

Data hold time after rising edge on

DCLK

0ns

tSU

Data set up time before rising edge on

DCLK

5ns

tPOR

POR delay

100

Notes to Table 4–14:

(1)

These values are preliminary

(2)

Only the EPCS16 and EPCS64 devices support a

DCLK frequency up to 40 MHz.

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