RT3624LE datasheet(42/48 Pages) RICHTEK

42 / 48 page

RT3624LE

is a registered trademark of Richtek Technology Corporation

www.richtek.com

DS3624LE-00

April

2022

Load

Trigger UD

PWM

w/ UD

PWM

w/o UD

Figure 21. Undershoot Suppression Behavior in Single Phase

Over-Current Protection (OCP)

The RT3624LE has sum OCP mechanisms and the threshold of sum OCP for PS0 is defined as

ISUM_OC,PS0=KSOCP×VIMON

ICCMAX×

RCS

DCR

RIMON,EQ

ISUM_OC,PS1,2,3=KSOCP1×VIMONICCMAX×

RCS

DCR

RIMON,EQ

ICCMAX<40, KSOCP=KSOCP1=1.6

ICCMAX>=40, KSOCP=1.3, KSOCP1=

phase number x KSOCP

While

RIMON,EQ

designed

exactly

meet

VIMONICCMAX=ICCMAX register value×

DCR

680Ω

×RIMON,EQ

ICCMAX register value=ICCMAX, and VIMONICCMAX=0.2V, 0.4V or 0.8V according to ICCMAX.

Sum OCP threshold can be simplified as ISUM_OC,PS0 =KSOCP×ICCMAX and ISUM_OC,PS1,2,3 =KSOCP1×ICCMAX. Note

that the modification of ICCMAX register value cannot change sum OCP threshold.

While inductor current above sum OCP threshold lasts 40

µs, controller de-asserts VR_READY and latches PWM in

tri-state to turn off high-side and low-side power MOSFETs. Sum OCP is masked during DV

ID period plus 80μs after

VID settles. It's also masked

when VID = 0V condition.

RT3624LE Datasheet(PDF) 42 Page - Richtek Technology Corporation

RT3624LE Datasheet(HTML) 42 Page - Richtek Technology Corporation

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