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RT3624LE Datasheet(PDF) 10 Page - Richtek Technology Corporation |
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RT3624LE Datasheet(HTML) 10 Page - Richtek Technology Corporation |
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10 / 48 page  RT3624LE Copyright © 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation www.richtek.com DS3624LE-00 April 2022 10 Parameter Symbol Test Conditions Min Typ Max Unit VREF VREF Voltage VVREF Normal operation 0.59 0.6 0.61 V VREF SPS Voltage VVREF_SPS Normal operation 1.2 1.3 1.4 V ADC Digital IMON Set GTUS dVIMON_ICCMAX VIMON − VREF = 0.8V @ ICCMAX >=80A VIMON − VREF = 0.4V @ ICCMAX >=40A VIMON − VREF = 0.2V @ ICCMAX <40A -- 255 -- Decimal VCCSA dVIMONA_ICCMAX VIMONA − VREF = 0.4V @ ICCMAX >=40A VIMONA − VREF = 0.2V @ ICCMAX <40A -- 255 -- Decimal AUX dVIMON_AUX_IC CMAX VIMON_AUX-VREF=1.6V -- 255 -- Decimal PSYS Maximum Input Voltage PSYS VPSYS = 1.6V -- 255 -- Decimal VSYS Maximum Input Voltage VSYS VIN/VSYS=24V -- 255 -- Decimal Averaging Period of IMON tIMON -- 150 -- µs Averaging Period of TSEN tTSEN -- 600 -- µs TSEN Voltage Threshold to Pull Low VR_HOT (Asserts VR_HOT ) TSEN_ VR_HOT_L V Within the range, VR_HOT = L 1.105 1.112 1.119 V TSEN Voltage Threshold to Pull High VR_HOT (De-Asserts VR_HOT ) TSEN_ VR_HOT_H V Within the range, VR_HOT = H 1.147 1.154 1.161 V TSEN Rises to Pull Low ALERT VTSEN_Status_H ALERT =Low 1.147 1.154 1.161 V TSEN Down to Pull Low ALERT VTSEN_Status_L ALERT =Low 1.196 1.201 1.208 V ITSEN TSEN Source Current ITSEN VTSEN = 1.6V 79.2 80 80.8 µA Input Power Domain Disable Voltage VPSYS VCC − 0.5 -- -- V Note 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θJA is measured under natural convection (still air) at TA = 25°C with the component mounted on a high effective-thermal-conductivity four-layer test board on a JEDEC 51-7 thermal measurement standard. θJC is measured at the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precautions are recommended. Note 4. The device is not guaranteed to function outside its operating conditions. |
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