RT3624LE datasheet(19/48 Pages) RICHTEK

19 / 48 page

RT3624LE

is a registered trademark of Richtek Technology Corporation

DS3624LE-00

April

2022

www.richtek.com

Table 1. Summary of Pin Setting Functions

Function Setting

Symbol

Description

SET1

Divider Register [4]

Setting VBOOT of GTUS rail

VBOOT[4]

VBOOT[4]=0, 0V

VBOOT[4]=1, non-zero

Divider Register[3:0] GTUS VR ICCMAX

ICCMAX[3:0]

According to Platform, set GTUS VR's

corresponding ICCMAX.

IXR Register[4:1]

VCCSA VR ICCMAX

ICCMAX_A[4:1]

According to Platform, set VCCSA

VR's corresponding ICCMAX.

SET2

Divider Register[4]

Setting VBOOT of VCCSA rail VBOOT_A[4]

VBOOT_A[4]=0, 0V

VBOOT_A[4]=1, non-zero

Divider Register[3]

Selectable VID table

VIDT[3]

VIDT[3]=0, VID1(0V~1.52V)

VIDT[3]=1, VID2(0V~2.74V)

Divider Register[2:0]

GTUS VR TON width setting

(switching frequency)

kTON[2:0]

According to required frequency,

select adaptive kTON parameter.

IXR Register[4:2]

AUX VR ICCMAX

ICCMAX_AUX[4:2]

According to Platform, set AUX VR's

corresponding ICCMAX.

IXR Register[1]

Enable zero load-line for

GTUS and VCCSA VR

0LL[1]

0LL[1]=0: Disable zero load-line

0LL[1]=1: Enable zero load-line

SET3

Divider Register[4:3]

GTUS VR undershoot

suppression

UDS[4:3]

To improve undershoot by applying a

positive offset at loading edge. Set

trigger level.

Divider Register[2]

DVID Fast slew rate

DVID fast_SR[2]

DVID fast_SR[2][0] = 00, 1/2*Fast_P

DVID fast_SR[2][0] = 01, 3/4*Fast_P

DVID fast_SR[2][0] = 10, Fast_P

DVID fast_SR[2][0 ]= 11, Fast_S

Divider Register[1]

GTUS VR DVID

voltage-compensation level

DVID_LIFT[1]

DVID_LIFT[1] = 0: 10uA

DVID_LIFT[1] = 1: 20uA

Current sink from FB pin

Divider Register[0]

DVID Fast slew rate

DVID fast_SR[0]

DVID fast_SR[2][0] = 00, 1/2*Fast_P

DVID fast_SR[2][0] = 01, 3/4*Fast_P

DVID fast_SR[2][0] = 10, Fast_P

DVID fast_SR[2][0 ]= 11, Fast_S

IXR Register[4:3]

VCCSA VR undershoot

suppression

UDS_A[4:3]

To improve undershoot by applying a

positive offset at loading edge. Set

trigger level.

IXR Register[2]

VR_HOT assertion during

DVID current limit

VR_HOT _DVID[2]

VR_HOT _DVID[2] = 0,Enable

VR_HOT _DVID[2] = 1,Disable

IXR Register[1]

VCCSA VR DVID

voltage-compensation level

DVID_LIFT_A[1]

DVID_LIFT_A[1] = 0: 10uA

DVID_LIFT_A[1] = 1: 20uA

Current sink from FB pin

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