WM8986GECOSLASHV datasheet(51/87 Pages) WOLFSON

51 / 87 page

Pre-Production

WM8986

PP, Rev 3.1, February 2007

In I2S mode, the MSB is available on the second rising edge of BCLK following a LRC transition. The

other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency

and sample rate, there may be unused BCLK cycles between the LSB of one sample and the MSB of

the next.

Figure 29 I

2S Audio Interface (assuming n-bit word length)

In DSP/PCM mode, the left channel MSB is available on either the 1st (mode B) or 2nd (mode A)

rising edge of BCLK (selectable by LRP) following a rising edge of LRC. Right channel data

immediately follows left channel data. Depending on word length, BCLK frequency and sample rate,

there may be unused BCLK cycles between the LSB of the right channel data and the next sample.

In device master mode, the LRC output will resemble the LRC pulse shown in Figure 30 and Figure

31. In device slave mode, Figure 32 and Figure 33, it is possible to use any length of LRC pulse less

than 1/fs, providing the falling edge of the LRC pulse occurs greater than one BCLK period before the

rising edge of the next LRC pulse.

Figure 30 DSP/PCM Mode Audio Interface (mode A, LRP=0, Master)

Figure 31 DSP/PCM Mode Audio Interface (mode B, LRP=1, Master)

WM8986GECO/V Datasheet(PDF) 51 Page - Wolfson Microelectronics plc