WM8986GECOSLASHV datasheet(54/87 Pages) WOLFSON

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WM8986

Pre-Production

PP, Rev 3.1, February 2007

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Sets the chip to be master over LRC

and BCLK

0 = BCLK and LRC clock are inputs

1 = BCLK and LRC clock are outputs

generated by the WM8986 (MASTER)

4:2

BCLKDIV

000

Configures the BCLK output frequency,

for use when the chip is master over

BCLK.

000 = divide by 1 (BCLK=SYSCLK)

001 = divide by 2 (BCLK=SYSCLK/2)

010 = divide by 4 (BCLK=SYSCLK/4)

011 = divide by 8 (BCLK=SYSCLK/8)

100 = divide by 16 (BCLK=SYSCLK/16)

101 = divide by 32 (BCLK=SYSCLK/32)

110 = reserved

111 = reserved

7:5

MCLKDIV

010

Sets the scaling for SYSCLK clock

output (under control of CLKSEL)

000 = divide by 1 (LRC=SYSCLK/128)

001 = divide by 1.5 (LRC=SYSCLK/192)

010 = divide by 2 (LRC=SYSCLK/256)

011 = divide by 3 (LRC=SYSCLK/384)

100 = divide by 4 (LRC=SYSCLK/512)

101 = divide by 6 (LRC=SYSCLK/768)

110 = divide by 8 (LRC=SYSCLK/1024)

111 = divide by 12 (LRC=SYSCLK/1536)

R6 (06h)

Clock

Generation

Control

CLKSEL

Controls the source of the clock for all

internal operation:

0 = MCLK

1 = PLL output

Table 33 Clock Control

AUDIO SAMPLE RATES

The WM8986 DAC limiter characteristics are sample rate dependent. SR should be set to the

correct sample rate or the closest value if the actual sample rate is not available.

If a sample rate that is not explicitly supported by the SR register settings is required then the closest

SR value to that sample rate should be chosen. The DAC limiter characteristics will scale

appropriately.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R7 (07h)

Additional

Control

3:1

000

Approximate sample rate (configures the

coefficients for the internal digital filters):

000 = 48kHz

001 = 32kHz

010 = 24kHz

011 = 16kHz

100 = 12kHz

101 = 8kHz

110-111 = reserved

Table 45 Sample Rate Control

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