Electronic Components Datasheet Search
  English  ▼

X  

Preview PDF HTML

WM8986GECO/V Datasheet(PDF) 68 Page - Wolfson Microelectronics plc

Part # WM8986GECO/V
Description  Multimedia DAC With Class D Headphone and Line Out
PDF  87 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  WOLFSON [Wolfson Microelectronics plc]
Direct Link  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8986GECO/V Datasheet(HTML) 68 Page - Wolfson Microelectronics plc

Back Button WM8986GECO/V Datasheet HTML 64Page - Wolfson Microelectronics plc WM8986GECO/V Datasheet HTML 65Page - Wolfson Microelectronics plc WM8986GECO/V Datasheet HTML 66Page - Wolfson Microelectronics plc WM8986GECO/V Datasheet HTML 67Page - Wolfson Microelectronics plc WM8986GECO/V Datasheet HTML 68Page - Wolfson Microelectronics plc WM8986GECO/V Datasheet HTML 69Page - Wolfson Microelectronics plc WM8986GECO/V Datasheet HTML 70Page - Wolfson Microelectronics plc WM8986GECO/V Datasheet HTML 71Page - Wolfson Microelectronics plc WM8986GECO/V Datasheet HTML 72Page - Wolfson Microelectronics plc Next Button
Zoom Inzoom in Zoom Outzoom out
 68 / 87 page
background image
WM8986
Pre-Production
w
PP, Rev 3.1, February 2007
68
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
5
WL8
0
Companding Control 8-bit mode
0=off
1=device operates in 8-bit mode
Digital Audio
Interfaces
4:3
DAC_COMP
00
DAC companding
00=off (linear mode)
01=reserved
10=µ-law
11=A-law
Digital Audio
Interfaces
2:0
000
Reserved
8
CLKSEL
1
Controls the source of the clock for all internal
operation:
0=MCLK
1=PLL output
Digital Audio
Interfaces
6 (06h)
7:5
MCLKDIV
010
Sets the scaling for either the MCLK or PLL
clock output (under control of CLKSEL)
000=divide by 1
001=divide by 1.5
010=divide by 2
011=divide by 3
100=divide by 4
101=divide by 6
110=divide by 8
111=divide by 12
Digital Audio
Interfaces
4:2
BCLKDIV
000
Configures the BCLK output frequency, for use
when the chip is master over BCLK.
000=divide by 1 (BCLK=MCLK)
001=divide by 2 (BCLK=MCLK/2)
010=divide by 4
011=divide by 8
100=divide by 16
101=divide by 32
110=reserved
111=reserved
Digital Audio
Interfaces
1
0
Reserved
0
MS
0
Sets the chip to be master over LRC and BCLK
0=BCLK and LRC clock are inputs
1=BCLK and LRC clock are outputs generated
by the WM8978 (MASTER)
Digital Audio
Interfaces
8
M128ENB
0
0 = low power mode enabled
1 = low power mode disabled
Additional
Control
7 (07h)
7:4
DCLKDIV
1000
Controls clock division from SYSCLK to
generate suitable class D clock.
Recommended class D clock frequency =
1.4MHz.
0000 = divide by 1
0010 = divide by 2
0011 = divide by 3
0100 = divide by 4
0101 = divide by 5.5
0110 = divide by 6
1000 = divide by 8
1001 = divide by 12
1010 = divide by 16
Class A / D
Headphone
Outputs



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com