WM8986GECOSLASHV datasheet(53/87 Pages) WOLFSON

53 / 87 page

Pre-Production

WM8986

PP, Rev 3.1, February 2007

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

MONO

Selects between stereo and mono

device operation:

0 = Stereo device operation

1 = Mono device operation. Data

appears in ‘left’ phase of LRC only.

DLRSWAP

Controls whether DAC data appears in

‘right’ or ‘left’ phases of LRC clock:

0 = DAC left data appear in ‘left’ phase

of LRC and right data in 'right' phase

1 = DAC left data appear in ‘right’ phase

of LRC and right data in 'left' phase

4:3

FMT

Audio interface Data Format Select:

00 = Right Justified

01 = Left Justified

10 = I2S format

11 = DSP/PCM mode

6:5

Word length

00 = 16 bits

01 = 20 bits

10 = 24 bits

11 = 32 bits (see note)

LRC clock polarity

0 = normal

1 =inverted

LRP

DSP Mode – mode A/B select

0 = MSB is available on 2nd BCLK rising

edge after LRC rising edge (mode A)

1 = MSB is available on 1st BCLK rising

edge after LRC rising edge (mode B)

R4 (04h)

Audio

Interface

Control

BCP

BCLK polarity

0 = normal

1 = inverted

Table 32 Audio Interface Control

Note:

Right Justified Mode will only operate with a maximum of 24 bits. If 32-bit mode is selected the

device will operate in 24-bit mode.

AUDIO INTERFACE CONTROL

The register bits controlling audio format, word length and master / slave mode are summarised

below.

and LRC are outputs. The frequency of BCLK in master mode can be controlled with BCLKDIV. The

frequencies of BCLK and LRC are also controlled by MCLKDIV. The LRC sample rate is set to the

required values by MCLKDIV and the BCLK rate will be set accordingly to provide sufficient BCLKs

for that chosen sample rate. These clocks are divided down versions of master clock.

WM8986GECO/V Datasheet(PDF) 53 Page - Wolfson Microelectronics plc

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