WM8986GECOSLASHV datasheet(73/87 Pages) WOLFSON

73 / 87 page

Pre-Production

WM8986

PP, Rev 3.1, February 2007

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

34 (22h)

8:0

000000000

Reserved

35 (23h)

8:0

000000000

Reserved

8:5

0000

Reserved

PLL

PRESCALE

Divide MCLK by 2 before input to PLL

Master Clock

and Phase

Locked Loop

(PLL)

36 (24h)

3:0

PLLN[3:0]

1000

Integer (N) part of PLL input/output frequency

ratio. Use values greater than 5 and less than

13.

Master Clock

and Phase

Locked Loop

(PLL)

8:6

000

Reserved

37 (25h)

5:0

PLLK[23:18]

01100

Fractional (K) part of PLL1 input/output

frequency ratio (treat as one 24-digit binary

number).

Master Clock

and Phase

Locked Loop

(PLL)

38 (26h)

8:0

PLLK[17:9]

010010011

Fractional (K) part of PLL1 input/output

frequency ratio (treat as one 24-digit binary

number).

Master Clock

and Phase

Locked Loop

(PLL)

39 (27h)

8:0

PLLK[8:0]

011101001

Fractional (K) part of PLL1 input/output

frequency ratio (treat as one 24-digit binary

number).

Master Clock

and Phase

Locked Loop

(PLL)

8:4

00000

Reserved

41 (29h)

3:0

DEPTH3D

0000

Stereo depth

0000: 0% (minimum 3D effect)

0001: 6.67%

....

1110: 93.3%

1111: 100% (maximum 3D effect)

3D Stereo

Enhancement

8:3

0000 00

Reserved

POBCTRL

VMID independent current bias control

0 = Disable VMID independent current bias

1 = Enable VMID independent current bias

42 (2Ah)

1:0

Reserved

Analogue

Outputs

BYPL2RMIX

Left channel input PGA stage to right output

mixer

0 = not selected

1 = selected

Analogue

Outputs

43 (2Bh)

BYPR2LMIX

Right channel input PGA stage to Left output

mixer

0 = not selected

1 = selected

Analogue

Outputs

Reserved

RIN2INPPGA

Connect RIN pin to right channel input PGA

negative terminal.

0=RIN not connected to input PGA

1=RIN connected to right channel input PGA

amplifier negative terminal.

Input Signal

Path

44 (2Ch)

RIP2INPPGA

Connect RIP pin to right channel input PGA

amplifier positive terminal.

0 = RIP not connected to input PGA

1 = right channel input PGA amplifier positive

terminal connected to RIP (constant input

impedance)

Input Signal

Path

WM8986GECO/V Datasheet(PDF) 73 Page - Wolfson Microelectronics plc

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