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WM8986GECO/V Datasheet(PDF) 64 Page - Wolfson Microelectronics plc |
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WM8986GECO/V Datasheet(HTML) 64 Page - Wolfson Microelectronics plc |
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64 / 87 page ![]() WM8986 Pre-Production w PP, Rev 3.1, February 2007 64 REGISTER MAP ADDR B[15:9] DEFAULT VAL DEC HEX REGISTER NAME B8 B7 B6 B5 B4 B3 B2 B1 B0 (HEX) 0 00 Software Reset Software reset 1 01 Power manage’t 1 0 OUT4MIX EN OUT3MIX EN PLLEN 0 BIASEN BUFIOEN VMIDSEL [1:0] 000 2 02 Power manage’t 2 ROUT1EN LOUT1EN SLEEP BOOST ENR BOOST ENL INPGA ENR INPPGA ENL 0 0 000 3 03 Power manage’t 3 OUT4EN OUT3EN ROUT2EN LOUT2EN 0 RMIXEN LMIXEN DACENR DACENL 000 4 04 Audio Interface BCP LRP WL[1:0] FMT[1:0] DLRSWAP 0 MONO 050 5 05 Companding ctrl 0 0 0 WL8 DAC_COMP [1:0] 0 0 0 000 6 06 Clock Gen ctrl CLKSEL MCLKDIV[2:0] BCLKDIV[2:0] 0 MS 140 7 07 Additional ctrl M128ENB DCLKDIV[3:0] SR[2:0] SLOWCLK EN 080 8 08 GPIO Stuff GPIO1GP GPIO1GPU GPIO1GPD OPCLKDIV[2:0] GPIO1POL GPIO1SEL[2:0] 000 9 09 Jack detect control 0 0 JD_EN 0 0 0 0 0 0 000 10 0A DAC Control 0 0 SOFT MUTE 0 0 DACOSR 128 AMUTE DACRPOL DACLPOL 000 11 0B Left DAC digital Vol DACVU DACLVOL[7:0] 0FF 12 0C Right DAC dig’l Vol DACVU DACRVOL[7:0] 0FF 13 0D Jack Detect Control 0 JD_EN1[3:0] JD_EN0[3:0] 000 14 0E Reserved 000000000 000 15 0F Reserved 000000000 000 16 10 Reserved 000000000 000 18 12 EQ1 – low shelf EQ3DEN 0 EQ1C[1:0] EQ1G[4:0] 12C 19 13 EQ2 – peak 1 EQ2BW 0 EQ2C[1:0] EQ2G[4:0] 02C 20 14 EQ3 – peak 2 EQ3BW 0 EQ3C[1:0] EQ3G[4:0] 02C 21 15 EQ4 – peak 3 EQ4BW 0 EQ4C[1:0] EQ4G[4:0] 02C 22 16 EQ5 – high shelf 0 0 EQ5C[1:0] EQ5G[4:0] 02C 23 17 Class D Control CLASSDEN 0 0 0 0 10 0 0 008 24 18 DAC Limiter 1 LIMEN LIMDCY[3:0] LIMATK[3:0] 032 25 19 DAC Limiter 2 0 0 LIMLVL[2:0] LIMBOOST[3:0] 000 27 1B Reserved 000000000 000 28 1C Reserved 000000000 000 29 1D Reserved 000000000 000 30 1E Reserved 000000000 000 32 20 Reserved 000000000 000 33 21 Reserved 000000000 000 34 22 Reserved 000000000 000 35 23 Reserved 000000000 000 36 24 PLL N 0 0 0 0 PLLPRE SCALE PLLN[3:0] 008 37 25 PLL K 1 0 0 0 PLLK[23:18] 00C 38 26 PLL K 2 PLLK[17:9] 093 39 27 PLL K 3 PLLK[8:0] 0E9 41 29 3D control 0 0 0 0 0 DEPTH3D[3:0] 000 42 2A Biasing 0 0 0 0 0 0 POBCTRL 0 0 000 43 2B Beep control BYPL2 RMIX BYPR2 LMIX 0 0 0 0 0 0 0 000 44 2C Input ctrl 0 0 0 RIN2 INPPGA RIP2 INPPGA 0 0 LIN2 INPPGA LIP2 INPPGA 003 |
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