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WM8986GECO/V Datasheet(PDF) 63 Page - Wolfson Microelectronics plc |
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WM8986GECO/V Datasheet(HTML) 63 Page - Wolfson Microelectronics plc |
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63 / 87 page ![]() Pre-Production WM8986 w PP, Rev 3.1, February 2007 63 POWER MANAGEMENT SAVING POWER BY REDUCING OVERSAMPLING RATE The default mode of operation of the DAC digital filters is in 64x oversampling mode. Under the control of DACOSR128 the oversampling rate may be doubled. 64x oversampling results in a slight decrease in noise performance compared to 128x but lowers the power consumption of the device. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R10 (0Ah) DAC control 3 DACOSR128 0 DAC oversample rate select 0 = 64x (lowest power) 1 = 128x (best SNR) Table 37 DAC Oversampling Rate Selection LOW POWER MODE If only limited functionality is required, the WM8986 can be put into a low power mode. In this mode, the DSP core runs at half of the normal rate, reducing digital power consumption of the core by half. For DAC low power only, 3D enhancement with 2-Band equaliser functionality is permitted, where only Band 1 (low shelf) and Band 5 (high shelf) can be used. . REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R7 (07h) Additional Ctrl 8 M128ENB 0 0 = low power mode enabled 1 = low power mode disabled Table 38 DSP Core Low Power Mode Control The register settings for this low-power mode are detailed below. The device will not enter low power unless in this register configuration, regardless of M128ENB. For pop-free operation of the device it is recommended to change the M128ENB low power functionality only when both DACs are disabled, i.e. when DACENL=0 and DACENR=0. FUNCTION REGISTER BITS SETTING DESCRIPTION DAC low power M128ENB DACENL DACENR 0 1 1 Either or both of DACENL and DACENR must be set (mono or stereo mode) Table 39 DSP Core Low Power Mode Register Settings VMID The analogue circuitry will not operate unless VMID is enabled. The impedance of the VMID resistor string, together with the decoupling capacitor on the VMID pin will determine the start-up time of the VMID circuit. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1 (01h) Power management 1 1:0 VMIDSEL 00 Reference string impedance to VMID pin 00= off (250kΩ VMID to AGND1) 01=75kΩ 10=300kΩ 11=5kΩ Table 40 VMID Impedance Control BIASEN The analogue amplifiers will not operate unless BIASEN is enabled. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1 (01h) Power management 1 3 BIASEN 0 Analogue amplifier bias control 0 = disabled 1 = enabled Table 41 Analogue Bias Control |
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