DS26519G datasheet(80/310 Pages) MAXIM

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DS26519 16-Port T1/E1/J1 Transceiver

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9.9.11 Transmit Per-Channel Idle Code Generation

Channel data can be replaced by an idle code on a per-channel basis in the transmit and receive directions.

The Transmit Idle Code Definition Registers (TIDR1–32) are provided to set the 8-bit idle code for each channel.

The Transmit Channel Idle Code Enable registers (TCICE1–4) are used to enable idle code replacement on a per-

channel basis.

9.9.12 Receive Per-Channel Idle Code Insertion

Channel data can be replaced by an idle code on a per-channel basis in the transmit and receive directions. The

Receive Idle Code Definition Registers (RIDR1–32) are provided to set the 8-bit idle code for each channel. The

Receive Channel Idle Code Enable Registers (RCICE1–4) are used to enable idle code replacement on a per-

channel basis.

9.9.13 Per-Channel Loopback

The Per-Channel Loopback Enable Registers (PCL1–4) determine which channels (if any) from the backplane

should be replaced with the data from the receive side or in other words, off of the T1 or E1 line. If this loopback is

enabled, then transmit and receive clocks and frame syncs must be synchronized. One method to accomplish this

would be to tie RCLKn to TCLKn and RFSYNCn to TSYNCn. There are no restrictions on which channels can be

looped back or on how many channels can be looped back.

Each of the bit positions in PCL1–4) represents a DS0 channel in the outgoing frame. When these bits are set to a

one, data from the corresponding receive channel will replace the data on TSERn for that channel.

9.9.14 E1 G.706 Intermediate CRC-4 Updating (E1 Mode Only)

The DS26519 can implement the G.706 CRC-4 recalculation at intermediate path points. When this mode is

enabled, the data stream presented at TSERn will already have the FAS/NFAS, CRC multiframe alignment word,

and CRC-4 checksum in time slot 0. The user can modify the Sa-bit positions and this change in data content will

be used to modify the CRC-4 checksum. This modification, however, will not corrupt any error information the

original CRC-4 checksum may contain. In this mode of operation, TSYNCn must be configured to multiframe mode.

The data at TSERn must be aligned to the TSYNCn signal. If TSYNCn is an input then the user must assert

TSYNCn aligned at the beginning of the multiframe relative to TSERn. If TSYNCn is an output, the user must

multiframe align the data presented to TSERn. This mode is enabled with the TCR3.0 control bit (CRC4R). Note

that the E1 transmitter must already be enabled for CRC insertion with the TCR1.0 control bit (TCRC4). See Figure

9-17.

Figure 9-17. CRC-4 Recalculate Method

TSERn

XOR

CRC-4

CALCULATOR

EXTRACT

OLD CRC-4

CODE

INSERT

NEW CRC-4

CODE

MODIFY

Sa-BIT

POSITIONS

NEW Sa-BIT

DATA

TTIPn/TRINGn

DS26519G Datasheet(PDF) 80 Page - Maxim Integrated Products

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