DS26519G datasheet(44/310 Pages) MAXIM

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DS26519 16-Port T1/E1/J1 Transceiver

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9.8.1.1 Elastic Stores Initialization

There are two elastic store initializations that may be used to improve performance in certain applications: elastic

store reset and elastic store align. Both of these involve the manipulation of the elastic store’s read and write

pointers and are useful primarily in synchronous applications (RSYSCLKn/TSYSCLKn are locked to

RCLKn/TCLKn, respectively). The elastic store reset is used to minimize the delay through the elastic store. The

elastic store align bit is used to center the read/write pointers to the extent possible.

Table 9-4. Elastic Store Delay After Initialization

INITIALIZATION

DELAY

Receive Elastic Store Reset

RESCR.2

N bytes < Delay < 1 Frame + N bytes

Transmit Elastic Store Reset

TESCR.2

N bytes < Delay < 1 Frame + N bytes

Receive Elastic Store Align

RESCR.3

1/2 Frame < Delay < 1 1/2 Frames

Transmit Elastic Store Align

TESCR.3

1/2 Frame < Delay < 1 1/2 Frames

N = 9 for RSZS = 0; N = 2 for RSZS = 1

9.8.1.2 Minimum Delay Mode

Elastic store minimum delay mode may be used when the elastic store’s system clock is locked to its network clock

(i.e., RCLKn locked to RSYSCLKn for the receive side and TCLKn locked to TSYSCLKn for the transmit side).

RESCR enables the receive elastic store minimum delay mode. When enabled, the elastic stores will be forced to a

maximum depth of 32 bits instead of the normal two-frame depth. This feature is useful primarily in applications that

interface to a 2.048MHz bus. Certain restrictions apply when minimum delay mode is used. In addition to the

restriction mentioned above, RSYNCn must be configured as an output when the receive elastic store is in

minimum delay mode, and TSYNCn must be configured as an output when transmit minimum delay mode is

enabled. In this mode, the SYNC outputs are always in frame mode (multiframe outputs are not allowed). In a

typical application RSYSCLKn and TSYSCLKn are locked to RCLKn, and RSYNCn (frame output mode) is

connected to TSSYNCIOn (frame input mode). The slip zone select bit (RSZS at RESCR.4) must be set to 1. All

the slip contention logic in the framer is disabled (since slips cannot occur). On power-up after the RSYSCLKn and

TSYSCLKn signals have locked to their respective network clock signals, the elastic store reset bit (RESCR.2)

should be toggled from a zero to a one to ensure proper operation.

9.8.1.3 Additional Receive Elastic Store Information

If the receive-side elastic store is enabled, then the user must provide either a 1.544MHz or 2.048MHz clock at the

RSYSCLKn pin. See Section 9.8.2 for higher rate system clock applications. The user has the option of either

providing a frame/multiframe sync at the RSYNCn pin or having the RSYNCn pin provide a pulse on

frame/multiframe boundaries. If signaling reinsertion is enabled, the robbed-bit signaling data is realigned to the

multiframe sync input on RSYNCn. Otherwise, a multiframe sync input on RSYNCn is treated as a simple frame

boundary by the elastic store. The framer will always indicate frame boundaries on the network side of the elastic

store via the RFSYNCn output whether the elastic store is enabled or not. Multiframe boundaries will always be

indicated via the RMSYNCn output. If the elastic store is enabled, then RMSYNCn will output the multiframe

boundary on the backplane side of the elastic store. When the device is receiving T1 and the backplane is enabled

for 2.048MHz operation, the RMSYNCn signal will output the T1 multiframe boundaries as delayed through the

elastic store. When the device is receiving E1 and the backplane is enabled for 1.544MHz operation, the

RMSYNCn signal will output the E1 multiframe boundaries as delayed through the elastic store.

If the user selects to apply a 2.048MHz clock to the RSYSCLKn pin, the user can use the backplane blank channel

select registers (RBCS1–4) to determine which channels will have the data output at RSERn forced to all ones.

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