AM2732 datasheet(65/114 Pages) TI1

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Table 6-13. SPI Master Mode Switching Characteristics (CLOCK PHASE = 0, SPICLK = output,

SPISIMO = output, and SPISOMI = input)

(1)(3) (continued)

see Figure 6-5 and Figure 6-6

NO.

PARAMETER

MIN

TYP

MAX UNIT

tC2TDELAY

Setup time CS active until SPICLK

high

(clock polarity = 0)

(5)

CSHOLD = 0

(C2TDELAY+2)*

tc(VCLK) – 7.5

(C2TDELAY+2)

* tc(VCLK) + 7

CSHOLD = 1

(C2TDELAY +3)

* tc(VCLK) – 7.5

(C2TDELAY+3)

* tc(VCLK) + 7

Setup time CS active until SPICLK low

(clock polarity = 1)

(5)

CSHOLD = 0

(C2TDELAY+2)*

tc(VCLK) – 7.5

(C2TDELAY+2)

* tc(VCLK) + 7

CSHOLD = 1

(C2TDELAY +3)

* tc(VCLK) – 7.5

(C2TDELAY+3)

* tc(VCLK) + 7

tT2CDELAY

Hold time, SPICLK low until CS inactive (clock polarity =

(5)

0.5*tc(SPC)M +

(T2CDELAY +

1) *tc(VCLK) – 7

0.5*tc(SPC)M +

(T2CDELAY +

1) * tc(VCLK) +

7.5

Hold time, SPICLK high until CS inactive (clock polarity =

(5)

0.5*tc(SPC)M +

(T2CDELAY +

1) *tc(VCLK) – 7

0.5*tc(SPC)M +

(T2CDELAY +

1) * tc(VCLK) +

7.5

Table 6-14. SPI Master Mode Timing Requirements (CLOCK PHASE = 0, SPICLK = output,

SPISIMO = output, and SPISOMI = input)

(1)(3)

see Figure 6-5

NO.

PARAMETER

MIN

TYP

MAX UNIT

tsu(SOMI-

SPCL)M

Setup time, SPISOMI before SPICLK low

(clock polarity = 0)

(4)

tsu(SOMI-

SPCH)M

Setup time, SPISOMI before SPICLK high

(clock polarity = 1)

(4)

th(SPCL-

SOMI)M

Hold time, SPISOMI data valid after SPICLK low

(clock polarity = 0)

(4)

th(SPCH-

SOMI)M

Hold time, SPISOMI data valid after SPICLK high

(clock polarity = 1)

(4)

(1)

The MASTER bit (SPIGCRx.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is cleared (where x= 0 or 1).

(2)

tc(MSS_VCLK) = main subsystem clock time = 1 / f(MSS_VCLK). For more details, see the Technical Reference Manual.

(3)

When the SPI is in Master mode, the following must be true: For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(MSS_VCLK) ≥ 25 ns,

where PS is the prescale value set in the SPIFMTx.[15:8] register bits. For PS values of 0: tc(SPC)M = 2tc(MSS_VCLK) ≥ 25 ns.

(4)

The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

(5)

C2TDELAY and T2CDELAY is programmed in the SPIDELAY register.

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AM2732, AM2732-Q1

SWRS245B – DECEMBER 2021 – REVISED DECEMBER 2023

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