AD9937 datasheet(20/44 Pages) AD

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AD9937

SYSTEM OVERVIEW

Figure 8 shows the typical system block diagram for the AD9937.

The CCD output is processed by the AD9937’s AFE circuitry,

which consists of a CDS, VGA, black level clamp, and A/D

converter. The digitized pixel information is sent to the digital

image processor chip, which performs the postprocessing and

compression. To operate the CCD, all CCD timing parameters

are programmed into the AD9937 from the system micropro-

cessor, through the 3-wire serial interface. From the system

master clock, VCKM provided by the image processor or exter-

nal crystal, the AD9937 generates all of the CCD’s horizontal

and vertical clocks and all internal AFE clocks.

CCD

BUFFER

VOUT

AD9937

ADCOUT

DATA

DIGITAL IMAGE

PROCESSING

ASIC

TIMING

GENERATOR

V-DRIVE

CCDIN

SERIAL

INTERFACE

DIGITAL

OUTPUTS

CCD

TIMING

0.1 F

CIN

Figure 8. Typical System Block Diagram, Master Mode

The H-drivers for H1(A–D) and H2(A,B), and RS are included

in the AD9937, allowing these clocks to be directly connected

to the CCD. H-drive voltage of up to 3.6 V is supported. An

external V-driver is required for the vertical transfer clocks and

sensor gate pulses.

Figure 9 shows the horizontal and vertical counter dimensions

for the AD9937. All internal horizontal and vertical clocking is

programmed using these dimensions to specify line and pixel

locations.

12-BIT HORIZONTALCOUNTER = 4096 PIXELS MAX

MAXIMUM FIELD DIMENSIONS

Figure 9. Horizontal and Vertical Counters

MAX VD LENGTH IS 2048 LINES

MAX HD LENGTH IS 4095 PIXELS

VCKM

Figure 10. Maximum VD/HD Dimensions

AD9937 Datasheet(PDF) 20 Page - Analog Devices

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